ICS853111-01 Datasheet | ICST

.. Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER Features - 9 differential 3.3V LVPECL / ECL outputs - 1 differential LVPECL input pair - PLCK, n PLCK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL - Maximum output frequency: >2GHz (typical) - Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on n PCLK input - Additive phase jitter, RMS: 0.03ps (typical) - Output skew: 35ps (maximum) - Part-to-part skew: 300ps (maximum) - Propagation delay: 675ps (maximum) - LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V - ECL mode operating voltage supply range: VCC = 0V, VEE = -3V to -3.8V - -40°C to 85°C ambient operating temperature - Lead-Free package Ro HS pliant GENERAL DESCRIPTION The ICS853111-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL/ECL Hi Per Clock S™ Fa n o u t B u f fe r a n d a m e m b e r o f t h e Hi Per Clock S ™ family of High Performance Clock Solutions from ICS. The PCLK, n PCLK pair can accept LVPECL, CML and SSTL differential input levels. The ICS853111-01 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853111-01 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM PCLK n PCLK Q0 n Q0 Q1 n Q1 Q2 n Q2 Q3 n Q3 Q4 n Q4 V BB Q5 n Q5 Q6 n Q6 Q7 n Q7 Q8 n Q8 PIN ASSIGNMENT VCCO n Q0 n Q1 n Q2 Q0 Q1 Q2 25 VEE nc PCLK VCC n PCLK VBB nc 26 27 28 1 2 3 4 5 n Q8 19 18 17 16 Q3 n Q3 Q4 VCCO n Q4 Q5 n Q5 15 14 13 12 Q8 7 n...