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M1025 - (M1025 / M1026) VCSO BASED CLOCK PLL

Description

The M1025/26 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation.

The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates.

Features

  • Figure 1: Pin Assignment Example I/O Clock Frequency Combinations Using M1025-11-155.5200 or M1026-11-155.5200 Input Reference Clock (MHz) (M1025) (M1026) GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN 1 2 3 4 5 6 7 8 9 PLL Ratio (Pin Selectable) (M1025) (M1026) Output Clock (MHz) (Pin Selectable) 19.44 or 38.88 77.76 155.52 622.08 8 or 4 2 1 0.25 155.52 or 77.76 Table 1: Example I/O Clock Frequency Combinations.

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Datasheet Details

Part number M1025
Manufacturer ICST
File Size 366.45 KB
Description (M1025 / M1026) VCSO BASED CLOCK PLL
Datasheet download datasheet M1025 Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com Integrated Circuit Systems, Inc. Product Data Sheet M1025/26 VCSO BASED CLOCK PLL WITH AUTOSWITCH PIN ASSIGNMENT (9 x 9 mm SMT) MR_SEL3 GND NC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC MR_SEL2 MR_SEL0 MR_SEL1 LOL NBW VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 GENERAL DESCRIPTION The M1025/26 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5Gb data rates. It can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode.
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