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W48S87-04 Datasheet Preview

W48S87-04 Datasheet

Spread Spectrum 3 DIMM Desktop Clock

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Preliminary Information
W48S87-04
Spread Spectrum 3 DIMM Desktop Clock
Features
• Outputs
- 4 CPU Clock (2.5V or 3.3V, 50 to 83.3MHz)
- 7 PCI (3.3V)
- 1 48MHz for USB (3.3V)
- 1 24MHz for Super I/O (3.3V)
- 2 REF (3.3V)
- 1 IOAPIC (2.5V or 3.3V)
- 12 SDRAM
• Serial data interface provides additional frequency selec-
tion, individual clock output disable, and other functions
• Smooth transition supports dynamic frequency assignment
• Frequency selection not affected during power down/up
cycle
• Supports a variety of power saving options
• 3.3V operation
• Available in 48-pin SSOP (300 mils)
Key Specifications
±0.5% Spread Spectrum Modulation:
±0.5%
Jitter (cycle-to-cycle):
250ps
Duty Cycle:
45-55%
1-4ns CPU-PCI skew
250ps PCI-PCI or CPU-CPU skew
Figure 1 Block Diagram
SDATA
SCLOCK
X1
X2
CPU3.3#_2.5
FS0
FS1
FS2
CPU_STOP#
PWR_DWN#
Serial Port
XTAL OSC
Device
Control
PLL Ref
Freq
VDD1
CPU Clock
Mode Control
Freq
Select
I/O
MODE
REF0/CPU3.3#_2.5
REF1(CPU_STOP#)
VDDL1
PLL1
Stop
Clock
Cntrl
IOAPIC
VDDL2
4 CPU0:3
VDD3
12 SDRAM0:11
÷2 VDD2
I/O PCI_F/FS1
I/O PCI0/FS2
4 PCI1:4
Power Down MODE
Control
PCI5(PWR_DWN#)
VDD1
PLL2
÷2
÷4
I/O 48MHZ/FS0
I/O 24MHZ/MODE
Table 1 Order Information
Part Number
W48S87
Freq. Mask Code
04
Package
H = SSOP (300 mils)
Table 2 Pin Selectable Frequency (Note)
Input Address
FS2 FS1 FS0
000
001
010
011
100
101
110
111
CPU, SDRAM
Clocks (MHz)
50.0
75.0
83.3
68.5
55.0
75.0
60.0
66.8
PCI Clocks
(MHz)
25.0
32.0
41.65
34.25
27.5
37.5
30.0
33.4
Note: Additional frequency selections provided by serial data inter-
face; refer to Table 6 on page 8.
Figure 2 Pin Diagram
VDD1
REF0/CPU3.3#_2.5
GND
X1
X2
VDD2
PCI_F/FS1
PCI0/FS2
GND
PCI1
PCI2
PCI3
PCI4
VDD2
PCI5(PWR_DWN#)
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDL1
47 IOAPIC
46 REF1(CPU_STOP#)
45 GND
44 CPU0
43 CPU1
42 VDDL2
41 CPU2
40 CPU3
39 GND
38 SDRAM0
37 SDRAM1
36 VDD3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDD3
29 SDRAM6
28 SDRAM7
27 GND
26 48MHZ/FS0
25 24MHZ/MODE
Note: Signal names in parenthesis denotes function is selectable
through mode pin register strapping.
April 1998
Revision 0.4
IC WORKS · 101 Nicholson Lane · San Jose, CA 95134-1359 · (408) 922-0202




IC WORKS

W48S87-04 Datasheet Preview

W48S87-04 Datasheet

Spread Spectrum 3 DIMM Desktop Clock

No Preview Available !

Preliminary Information
W48S87-04
Overview
The W48S87-04, a motherboard clock synthesizer, can pro-
vide either a 2.5V or 3.3V CPU clock swing making it suitable
for a variety of CPU options. Twelve SDRAM clocks are pro-
vided in phase with the CPU clock outputs. This provides
clock support for up to three SDRAM DlMMs. Fixed output
frequency clocks are provided for other system functions.
Functional Description
I/O Pin Operation
Pins 2, 7, 8, 25 and 26 are dual purpose l/O pins. Upon
power up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after power
up, the logic state of these pins is latched and the pins then
become clock outputs. This feature reduces device pin count
by combining clock outputs with input select pins.
An external 10 kohm "strapping" resistor is connected
between each l/O pin and ground or VDD3. Connection to
ground sets a latch to "0", connection to VDD3 sets a latch to
"1". Figure 3 and Figure 4 show two suggested methods for
strapping resistor connection.
Upon W48S87-04 power up, the first 2ms of operation is
used for input logic selection. During this period, these dual
purpose I/O pins are tristated, allowing the output strapping
resistor on each l/O pin to pull the pin and its associated
capacitive clock load to either a logic high or low state. At the
end of the 2ms period, the established logic 0 or 1 condition
of each l/O is pin is then latched. Next the output buffers are
enabled which converts the l/O pins into operating clock out-
puts. The 2ms timer is started when VDD reaches 2.0V. The
input bits can only be re-set by turning VDD off and then back
on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of both clock outputs is <40 ohms (nominal) which is
minimally affected by the 10 kohm strap to ground or VDD.
As with the series termination resistor, the output strapping
resistor should be placed as close to the l/O pin as possible in
order to keep the interconnecting trace short. The trace from
the resistor to ground or VDD should be kept less than two
inches in length to prevent system noise coupling during
input logic sampling.
When the clock outputs are enabled following the 2ms input
period, target (normal) output frequency is delivered assum-
ing that VDD has stabilized. If VDD has not yet reached full
value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Figure 3 Input Logic Selection Through Resistor Load Option
VDD
W48S87-04
Power-on
Reset
Timer
Output
Buffer
Output Tristate
Hold
Output
Low
QD
Data
Latch
10k
(Load Option 1)
10k
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
22Clock Load
Page 2
Spread Spectrum 3 DIMM Desktop Clock
Revision 0.4


Part Number W48S87-04
Description Spread Spectrum 3 DIMM Desktop Clock
Maker IC WORKS
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