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Integrated Device Technology Electronic Components Datasheet

9DBL0452 Datasheet

4-Output 3.3V PCIe Zero-delay Buffer

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4-Output 3.3V PCIe Zero-delay
Buffer
9DBL0442 / 9DBL0452
DATASHEET
Description
The 9DBL0442 / 9DBL0452 devices are 3.3V members of
IDT's Full-Featured PCIe family. The 9DBL0442 / 9DBL0452
supports PCIe Gen1-4 Common Clocked (CC) and PCIe
Separate Reference Independent Spread (SRIS) systems. It
offers a choice of integrated output terminations providing
direct connection to 85or 100transmission lines. The
9DBL04P2 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
4 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0442 default ZOUT = 100
9DBL0452 default ZOUT = 85
9DBL04P2 factory programmable defaults
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2-3 SRIS in fan-out mode
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Features/Benefits
Direct connection to 100(xx42) or 85(xx52)
transmission lines; saves 16 resistors compared to
standard PCIe devices
132mW typical power consumption in PLL mode;
eliminates thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
Customer defined SMBus power up default can be
programmed into P2 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
5 × 5 mm 32-VFQFPN package; minimal board space
Block Diagram
Note: Resistors default to internal on xx42/xx52 devices. P2 devices have programmable default impedances on an output-by-output basis.
9DBL0442 / 9DBL0452 FEBRUARY 22, 2017
1
©2017 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

9DBL0452 Datasheet

4-Output 3.3V PCIe Zero-delay Buffer

No Preview Available !

9DBL0442 / 9DBL0452 DATASHEET
Pin Configuration
^vHIBW_BYPM_LOBW# 1
FB_DNC 2
FB_DNC# 3
VDDR3.3 4
CLK_IN 5
CLK_IN# 6
NC 7
GNDDIG 8
32 31 30 29 28 27 26 25
24 vOE2#
23 DIF2#
9DBL0442/52/P2
connect epad to
GND
22 DIF2
21 VDDA3.3
20 NC
19 vOE1#
18 DIF1#
17 DIF1
9 10 11 12 13 14 15 16
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor (biased
to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
CKPWRGD_PD# CLK_IN
SMBus
OE bit
OEx# Pin
DIFx/DIFx#
True O/P Comp. O/P
0
X
X
X
Low1
Low1
1
Running
1
0
Running
Running
1
Running
1
1
Disabled1
Disabled1
1
Running
0
X
Disabled1
Disabled1
1. The output state is set by B11[1:0] (Low/Low default)
2. Input polarities defined as default values for xx42/xx52 devices.
3. If Bypass mode is selected, the PLL will be off, and outputs will be running.
PLL
Off
On3
On3
On3
Power Connections
Pin Number
VDD
GND
4 33
11 8
15,25
33
21 33
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
2
FEBRUARY 22, 2017


Part Number 9DBL0452
Description 4-Output 3.3V PCIe Zero-delay Buffer
Maker IDT
PDF Download

9DBL0452 Datasheet PDF





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