9ZML1232 Key Features
- Low-Power (LP) HCSL Output Pairs
- Fixed feedback path; 0ps input-to-output delay
- 9 Selectable SMBus addresses; multiple devices can
- Separate VDDIO for outputs; allows maximum power
- PLL or bypass mode; PLL can dejitter ining clock
- Hardware or Software-selectable PLL BW; minimizes
- Spread spectrum patible; tracks spreading input
- SMBus Interface; unused outputs can be disabled
- Differential outputs are Low/Low in power down
- Cycle-to-cycle jitter <50ps
