9ZXL1930D Datasheet | IDT

Description The 9ZXL1930D / 9ZXL1950D are second-generation, enhanced-performance DB1900Z-derivative differential buffers. The parts are pin-patible upgrades to the 9ZXL1930B and 9ZXL1950B, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. In fanout mode, the devices meet the DB2000Q additive phase jitter specification. PCIe Clocking Architectures - mon Clocked (CC) - Independent Reference (IR) with and without spread spectrum Typical Applications - Servers - Storage - Networking - SSDs Output Features - 19 Low-Power HCSL (LP-HCSL) output pairs (1930D) - 19 Low-Power HCSL (LP-HCSL) output pairs with 85Ω Zout (1950D) Features - LP-HCSL outputs; eliminate 38 resistors, save 65mm2 of area (1930D) - LP-HCSL outputs with 85Ω Zout; eliminate 76 resistors, save 130mm2 of area (1950D) - SMBus OE bits; software control of each output - 9 selectable SMBus addresses; multiple devices can share the same SMBus segment - Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies - Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle - Spread spectrum patible; tracks spreading input clock for EMI reduction - 10 × 10 mm 72-VFQFPN package; small board footprint Key Specifications - Cycle-to-cycle jitter: < 50ps - Output-to-output skew: < 50ps - Input-to-output delay: fixed at 0ps - Input-to-output delay variation: < 50ps - Additive phase jitter: PCIe Gen4 < 53fs rms - Additive phase jitter: IF-UPI < 70fs rms - Additive phase jitter: DB2000Q filter < 80fs rms Block Diagram VDDR VDDA VDD x3 VDDIO x6 PLL DIF_IN# DIF_IN FBOUT_NC# FBOUT_NC DIF18#...