DAC1005D750 Datasheet | IDT

Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating Rev. 05 - 2 July 2012 Product data sheet 1. General description The DAC1005D750 is a high-speed 10-bit dual channel Digital-to-Analog Converter (DAC) with selectable 4 or 8 interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1005D750 allows the plex I and Q inputs to be converted from Base Band (BB) to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. A 4 and 8 clock multiplier enables the DAC1005D750 to provide the appropriate internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use of an external high frequency clock. The voltage regulator enables adjustment of the output full-scale current. 2. Features and benefits - Dual 10-bit resolution - 750 Msps maximum update rate - IMD3: 74 d Bc; fs = 737.28 Msps; fo = 140 MHz - ACPR: 64 d Bc; 2-carrier WCDMA; fs = 737.28 Msps; fo = 153.6 MHz - Selectable 4 or 8 interpolation filters - Typical 1.2 W power dissipation at 4 interpolation, PLL off and 740 Msps - Input data rate up to 185 Msps - Power-down and Sleep modes - Very low noise cap-free integrated PLL - Differential scalable output current from 1.6 m A to 22 m A - 32-bit programmable NCO frequency - On-chip 1.29 V reference - Dual port or Interleaved data modes - External analog offset control (10-bit auxiliary DACs) - 1.8 V and 3.3 V power supplies - Internal digital offset control - LVDS patible clock - Inverse x / (sin x)...