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Integrated Device Technology Electronic Components Datasheet

ICS1526 Datasheet

Video Clock Synthesizer

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Integrated Device Technology, Inc.
ICS1526
Video Clock Synthesizer
General Description
The ICS1526 is a low-cost, high-performance
frequency generator. It is suited to general purpose
phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using IDT’s advanced low-voltage
CMOS mixed-mode technology, the ICS1526 is an
effective clock synthesizer that supports video
projectors and displays at resolutions from VGA to
beyond XGA.
The ICS1526 offers single-ended clock outputs to 110
MHz. The HSYNC_out, and VSYNC_out pins provide
the regenerated versions of the HSYNC and VSYNC
inputs synchronous to the CLK output.
The advanced PLL uses its internal programmable
feedback divider. The device is programmed by a
standard I2C-bus™ serial interface and is available in
a TSSOP16 package.
ICS1526 Functional Diagram
OSC
HSYNC
VSYNC
I2C
ICS1526
HSYNC_out
VSYNC_out
CLK
LOCK
Features
• Lead-free packaging (Pb-free)
• Low jitter (typical 27 ps short term jitter)
• Wide input frequency range
• 8 kHz to 100 MHz
• LVCMOS single-ended clock outputs
• Up to 110 MHz
• Uses 3.3 V power supply
• 5 Volt tolerant Inputs (HSYNC, VSYNC)
• Coast (ignore HSYNC) capability via VSYNC pin
• Industry standard I2C-bus programming interface
• PLL Lock detection via I2C or LOCK output pin
• 16-pin TSSOP package
Applications
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems
Pin Configuration (16-pin TSSOP)
VSSD
SDA
SCL
VSYNC
HSYNC
VDDA
VSSA
OSC
1
2
3
4
5
6
7
8
16 VDDD
15 VSSQ
14 VSYNC_out
13 VDDQ
12 CLK
11 HSYNC_out
10 LOCK
9 I2CADR
MDS 1526 P
IDT reserves the right to make changes in the preliminary device data
identified in this publication without notice. IDT advises its customers
to obtain the latest version of all device data to verify that information
being relied upon is current and accurate.
Revision 051310


Integrated Device Technology Electronic Components Datasheet

ICS1526 Datasheet

Video Clock Synthesizer

No Preview Available !

ICS1526 Data Sheet
Section 1 Overview
The ICS1526 is a user-programmable,
high-performance general purpose clock generator. It
is intended for graphics system line-locked and
genlocked applications and provides the clock signals
required by high-performance analog-to-digital
converters.
Figure 1-1 Simplified Block Diagram
Section 1 Overview
The ICS1526 has the ability to operate in line-locked
mode with the HSYNC input.
1.1 Phase-Locked Loop
The phase-locked loop has a very wide input frequency
range (8 kHz to 100 MHz). Not only is the ICS1526 an
excellent, general purpose clock synthesizer, but it is
also capable of line-locked operation. Refer to the
block diagram below.
OSC
HSYNC
Divider
3..129
VSYNC
PFD
CP
VCO
VCOD
2,4,8,16
FD
12..4103
CLK
Flip-flop
Flip-flop
HSYNC_out
VSYNC_out
Note: Polarity controls and other circuit elements are not shown in above diagram for simplicity
The heart of the ICS1526 is a voltage controlled
oscillator (VCO). The VCOs speed is controlled by the
voltage on the loop filter. This voltage will be described
later in this section.
The VCOs clock output is first passed through the VCO
Divider (VCOD). The VCOD allows the VCO to operate
at higher speeds than the required output clock.
NOTE: Under normal, locked operation the VCOD has
no effect on the speed of the output clocks, just the
VCO frequency.
The output of the VCOD is the full speed output
frequency seen on the CLK. This clock is then sent
through the 12-bit internal Feedback Divider (FD). The
feedback divider controls how many clocks are seen
during every cycle of the input reference.
The Phase Frequency Detector (PFD) then compares
the feedback to the input and controls the filter voltage
by enabling and disabling the charge pump. The
charge pump has programmable current drive and will
source and sink current as appropriate to keep the
input and the clock output aligned.
The input HSYNC and VSYNC can be conditioned by a
high-performance Schmitt-trigger by sharpening the
rising/falling edge.
The HSYNC_out and VSYNC_out signals are aligned
with the output clock (CLK) via a set of flip flops.
1.2 Output Drivers and Logic Inputs
The ICS1526 uses low-voltage TTL (LVTTL) inputs and
LVCMOS outputs, operating at the 3.3 V supply
voltage. The LVTTL inputs are 5 V tolerant.
The LVCMOS drive resistive terminations or
transmission lines.
1.3 Automatic Power-On Reset Detection
The ICS1526 has automatic power-on reset detection
(POR) circuitry and it resets itself if the supply voltage
drops below threshold values. No external connection
to a reset signal is required.
MDS 1526 P
2
Revision 051310
In te grated Devi ce Te ch nol ogy, Inc. ww w.idt. c o m Te c h Su p p o rt : w w w.i dt . c o m / g o / c l o c k h e l p ( IDT™/ ICS™)


Part Number ICS1526
Description Video Clock Synthesizer
Maker IDT
Total Page 11 Pages
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