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Integrated Device Technology Electronic Components Datasheet

ICS574 Datasheet

LOW SKEW BUFFER

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ZERO DELAY, LOW SKEW BUFFER
DATASHEET
ICS574
Description
The ICS574 is a low jitter, low-skew, high performance
PLL-based zero delay buffer for high speed applications.
Based on IDT’s proprietary low jitter Phase Locked Loop
(PLL) techniques, the device provides four low skew
outputs at speeds up to 160 MHz at 3.3 V. When one of the
outputs is connected directly to FBIN, the rising edge of
each output is aligned with the rising edge of the input
clock. External delay elements connected in the feedback
loops will cause the outputs to occur before the inputs by
the amount of propagation delay of the external element.
Block Diagram
Features
Packaged in 8 pin narrow SOIC, Pb (lead) free
Zero input-to-output delay
Four 1X outputs
Output to output skew is less than 150 ps
Output clocks up to 160 MHz at 3.3 V
External feedback path for output edge placement
Spread Smart™ technology works with spread spectrum
clock generators
Full CMOS outputs with 18 mA output drive capability at
TTL levels at 3.3 V
Advanced, low power, sub-micron CMOS process
Operating voltage from 3.0 to 5.5 V
Industrial temperature version available
FBIN
CLKIN
PLL
CLK1
CLK2
CLK3
CLK4
IDT™/ ICS™ ZERO DELAY, LOW SKEW BUFFER
1
ICS574
REV G 051310


Integrated Device Technology Electronic Components Datasheet

ICS574 Datasheet

LOW SKEW BUFFER

No Preview Available !

ICS574
ZERO DELAY, LOW SKEW BUFFER
Pin Assignment
CLKIN
CLK1
CLK2
GND
1
2
3
4
8 FBIN
7 CLK4
6 CLK3
5 VDD
ZDB
Pin Descriptions
Pin
Number
1
2, 3, 6, 7
4
5
8
Pin
Name
CLKIN
CLK1:4
GND
VDD
FBIN
Pin
Type
Input
Output
Power
Power
Input
Pin Description
Clock input. Connect to input clock source.
Clock Outputs (4).
Connect to ground.
Power supply. Connect both pins to same voltage (either 3.3 V or 5 V).
Feedback input.
IDT™/ ICS™ ZERO DELAY, LOW SKEW BUFFER
2
ICS574
REV G 051310


Part Number ICS574
Description LOW SKEW BUFFER
Maker IDT
Total Page 7 Pages
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