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ICS574 - LOW SKEW BUFFER

Description

The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications.

Based on IDT’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V.

Features

  • Packaged in 8 pin narrow SOIC, Pb (lead) free.
  • Zero input-to-output delay.
  • Four 1X outputs.
  • Output to output skew is less than 150 ps.
  • Output clocks up to 160 MHz at 3.3 V.
  • External feedback path for output edge placement.
  • Spread Smart™ technology works with spread spectrum clock generators.
  • Full CMOS outputs with 18 mA.

📥 Download Datasheet

Datasheet Details

Part number ICS574
Manufacturer IDT
File Size 124.19 KB
Description LOW SKEW BUFFER
Datasheet download datasheet ICS574 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ZERO DELAY, LOW SKEW BUFFER DATASHEET ICS574 Description The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on IDT’s proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element.
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