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ICS851S201I Datasheet

2:2 Differential-to-HCSL Multiplexer

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2:2 Differential-to-HCSL Multiplexer
with Low Input Level Alarm
ICS851S201I
Datasheet
Description
The ICS851S201I is a high-performance 2-input, 2-output
Differential-to-HCSL Multiplexer. The ICS851S201I operates up to
250MHz and accepts HCSL and other low level differential inputs
levels. Input level detection circuitry is available to flag input levels
that drops below a specified value and on the selected input. This
signal is latched until the status is reset via the alarm reset input.
The ICS851S201I is packaged in a small 3mm x 3mm 16 lead
VFQFPN package, making it ideal for use on space constrained
boards.
Features
Two differential HCSL output pairs
Two selectable differential clock input pairs
CLKx, nCLKx pairs can accept HCSL level inputs
Low level input detection on selected input (latched)
Maximum Input frequency: 250MHz
Output skew: 5ps (typical)
Propagation delay: 1.4ns (typical)
Additive RMS phase jitter at 133.33MHz (12kHz - 20MHz):
0.151ps (typical)
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
CLK0 Pulldown
nCLK0 Pullup/Pulldown
CLK1 Pulldown
nCLK1 Pullup/Pulldown
CLK_SEL Pulldown
IREF
LLAR Pulldown
0
1
Pin Assignment
Q0
nQ0
Q1
nQ1
LLA
16 15 14 13
CLK0 1
12 nQ0
nCLK0 2
11 Q0
CLK1 3
10 nQ1
nCLK1 4
9 Q1
5 6 78
ICS851S201I
16-Lead VFQFPN
Top View
ICS851S201I FEBRUARY 1, 2018
1 ©2018 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS851S201I Datasheet

2:2 Differential-to-HCSL Multiplexer

No Preview Available !

ICS851S201I Datasheet
2:2 DIFFERENTIAL-TO-HCSL MULTIPLEXER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
1
CLK0
Input
Pulldown
2
nCLK0
Input
Pullup/
Pulldown
3
CLK1
Input
Pulldown
4
nCLK1
Input
Pullup/
Pulldown
5, 13
VDD Power
6
LLAR
Input
Pulldown
7
8, 16
9, 10
11, 12
LLA
GND
Q1, nQ1
Q0, nQ0
Output
Power
Output
Output
Description
Non-inverting differential HCSL clock input.
Inverting differential HCSL clock input. VDD/2 default when left floating.
Non-inverting differential HCSL clock input.
Inverting differential HCSL clock input. VDD/2 default when left floating.
Positive supply pins.
Low Level Alarm Reset. When HIGH, resets LLA latch. Must be LOW to
allow LLA to set. LVCMOS/LVTTL interface levels.
Low Level Alarm. When HIGH, low level input has been detected on
selected differential input (latched).
Power supply ground.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
14
IREF
Input
External fixed precision resistor (475from this pin to ground provides a
reference current used for differential current-mode Qx, nQx clock outputs.
15
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
k
ICS851S201I FEBRUARY 1, 2018
2 ©2018 Integrated Device Technology, Inc.


Part Number ICS851S201I
Description 2:2 Differential-to-HCSL Multiplexer
Maker IDT
Total Page 16 Pages
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