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Integrated Device Technology Electronic Components Datasheet

ICS854S202I Datasheet

Differential-to-LVDS Multiplexer

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12:2, Differential-to-LVDS Multiplexer
ICS854S202I
DATASHEET
General Description
The ICS854S202I is a 12:2 Differential-to-LVDS Clock Multiplexer
which can operate up to 3GHz. The ICS854S202I has twelve select-
able differential clock inputs, any of which can be independently rout-
ed to either of the two LVDS outputs. The CLKx, nCLKx input pairs
can accept LVPECL, LVDS, CML levels. The fully differential architec-
ture and low propagation delay make it ideal for use in clock distribu-
tion circuits.
Features
• Two differential 3.3V LVDS clock outputs
• Twelve selectable differential clock inputs
• CLKx, nCLKx pairs can accept the following differential input levels:
LVPECL, LVDS, CML
• Maximum output frequency: 3GHz
• Propagation delay: 1.1ns (maximum)
• Input skew: 100ps (maximum)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS (12kHz – 20MHz): 0.16ps (typical)
• Full 3.3V operating supply mode
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
SELA_[3:0] Pulldown
CLK0 Pulldown
nCLK0 Pullup/Pulldown
CLK1 Pulldown
nCLK1 Pullup/Pulldown
CLK2 Pulldown
nCLK2 Pullup/Pulldown
CLK3 Pulldown
nCLK3 Pullup/Pulldown
CLK4 Pulldown
nCLK4 Pullup/Pulldown
CLK5 Pulldown
nCLK5 Pullup/Pulldown
CLK6 Pulldown
nCLK6 Pullup/Pulldown
CLK7 Pulldown
nCLK7 Pullup/Pulldown
CLK8 Pulldown
nCLK8 Pullup/Pulldown
CLK9 Pulldown
nCLK9 Pullup/Pulldown
CLK10 Pulldown
nCLK10 Pullup/Pulldown
CLK11 Pulldown
nCLK11 Pullup/Pulldown
SELB_[3:0] Pulldown
4
4
QA
nQA
Pullup OEA
CLK2
nCLK2
SELA_0
SELA_1
VDD
QA
nQA
GND
SELA_2
SELA_3
CLK3
nCLK3
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3
4
ICS854S202I
34
33
5
48-Pin LQFP
32
6 7mm x 7mm x 1.4mm 31
7
package body
30
8
Y Package
29
9
10
Top View
28
27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
CLK9
nCLK9
SELB_0
SELB_1
VDD
QB
nQB
GND
SELB_2
SELB_3
CLK8
nCLK8
QB
nQB
Pullup OEB
ICS854S202AYI REVISION A JANUARY 21, 2013
1
©2013 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS854S202I Datasheet

Differential-to-LVDS Multiplexer

No Preview Available !

ICS854S202I Data Sheet
12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
CLK2
Input
Pulldown
Non-inverting differential clock input.
2
nCLK2
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
3, SELA_0,
4,
9,
SELA_1,
SELA_2,
Input
Pulldown
Clock select pins for Bank A output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3B.
10 SELA_3
5, 18, 32, 43
6, 7
VDD
QA, nQA
Power
Output
Power supply pins.
Clock outputs. LVDS interface levels.
8, 15, 22, 29,
39, 46
GND
Power
Power supply ground.
11
CLK3
Input
Pulldown
Non-inverting differential clock input.
12
nCLK3
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
13
nCLK4
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
14
CLK4
Input
Pulldown
Non-inverting differential clock input.
16
nCLK5
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
17
CLK5
Input
Pulldown
Non-inverting differential clock input.
18, 43
19
VDD
OEA
Power
Input
Pullup
Positive supply pins.
Output enable pin. Controls enabling and disabling of QA, nQA
output pair. LVCMOS/LVTTL interface levels.
20
CLK6
Input
Pulldown
Non-inverting differential clock input.
21
nCLK6
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
23
CLK7
Input
Pulldown
Non-inverting differential clock input.
24
nCLK7
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
25
nCLK8
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
26
CLK8
Input
Pulldown
Non-inverting differential clock input.
27, SELB_3,
28,
33,
SELB_2,
SELB_1,
Input
Pulldown
Clock select pins for Bank B output pair. See Control Input Function
Table. LVCMOS/LVTTL interface levels. See Table 3C.
34 SELB_0
30, 31
nQB, QB
Output
Clock outputs. LVDS interface levels.
35
nCLK9
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
36
CLK9
Input
Pulldown
Non-inverting differential clock input.
37
nCLK10
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
38
CLK10
Input
Pulldown
Non-inverting differential clock input.
40
nCLK11
Input
Pullup/Pulldown Inverting differential clock input. VDD/2 default when left floating.
41
CLK11
Input
Pulldown
Non-inverting differential clock input.
42
OEB
Input
Pullup
Output enable pin. Controls enabling and disabling of QB, nQB
output pair. LVCMOS/LVTTL interface levels.
44
CLK0
Input
Pulldown
Non-inverting differential clock input.
ICS854S202AYI REVISION A JANUARY 21, 2013
2
©2013 Integrated Device Technology, Inc.


Part Number ICS854S202I
Description Differential-to-LVDS Multiplexer
Maker IDT
Total Page 17 Pages
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