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ICS8735I-21 - ZERO DELAY CLOCK GENERATOR

Datasheet Summary

Description

The ICS8735I-21 is a highly versatile 1:1 Differential-to3.3V LVPECL clock generator.

The CLK, nCLK pair can accept most standard differential input levels.

Features

  • One differential 3.3V LVPECL output pair, one differential feedback output pair.
  • Differential CLK, nCLK input pair.
  • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL.
  • Output frequency range: 31.25MHz to 700MHz.
  • Input frequency range: 31.25MHz to 700MHz.
  • VCO range: 250MHz to 700MHz.
  • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2.

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Datasheet Details

Part number ICS8735I-21
Manufacturer IDT
File Size 248.78 KB
Description ZERO DELAY CLOCK GENERATOR
Datasheet download datasheet ICS8735I-21 Datasheet
Additional preview pages of the ICS8735I-21 datasheet.

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Full PDF Text Transcription

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ICS8735I-21 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR GENERAL DESCRIPTION The ICS8735I-21 is a highly versatile 1:1 Differential-to3.3V LVPECL clock generator. The CLK, nCLK pair can accept most standard differential input levels. The ICS8735I-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes.
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