ICS9DB403D Datasheet | IDT

Description The ICS9DB403 is patible with the Intel DB400v2 Differential Buffer Specification. This buffer provides 4 PCI-Express Gen2 cloc ks. The ICS9DB403 is driven by a differential output pair from a CK410B+, CK505 or CK509B main cloc k generator. Features /Benefits - - Spread spectr um modulation toler ant, 0 to -0.5% do wn spread and +/- 0.25% center spread. Supports undr iven differential outputs in PD# and SRC_STOP# modes for power management. Output Features - - - - - 4 - 0.7V current-mode diff erential output pairs Supports zero delay buffer mode and f anout mode Bandwidth programming available 50-100 MHz operation in PLL mode 50-400 MHz operation in Bypass mode Key Specifications - - - - - - - Outputs cycle-cycle jitter < 50ps Outputs skew: 50ps Phase jitter: PCIe Gen1 < 86ps peak to peak Phase jitter: PCIe Gen2 < 3.0/3.1ps rms 28-pin SSOP/TSSOP pacakge Available in Ro HS pliant packaging Supports mercial (0 to +70°C) and Industrial (-40 to +85°C) temperature ranges Functional Block Diagram 24 -OE(6, 1) OE(6,5,2,1) SRC_IN SRC_IN# SPREAD PATIBLE PLL 4 M U X STOP LOGIC DIF(6,5,2,1) PD BYPASS#/PLL SDATA SCLK CONTROL LOGIC IREF Note: Polarities shown for OE_INV = 0. IDT® Four Output Differential Buffer for PCIe and Gen 1 and Gen 2 ICS9DB403D REV R 11/1/12 1 http://.. ICS9DB403D Four Output Differential Buffer for PCIe for Gen 1 and Gen 2 Pin Configuration VDDR SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# OE_1 DIF_2 DIF_2# VDD BYPAS S#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OE_INV = 0 VDDA GNDA IREF OE_INV VDD DIF_6 DIF_6# OE_6 DIF_5 DIF_5# VDD HIGH_BW# DIF_STOP# PD# VDDR SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# OE1# DIF_2 DIF_2# VDD BYPA SS#/PLL SCLK SDATA 1 2 3 4 5 6 7 82 9 10 11 12 13 14 28 27 26 25 24 23 22 1 20 19 18 17 16 15 OE_INV = 1 VDDA GNDA IREF OE_INV VDD DIF_6 DIF_6# OE6# DIF_5 DIF_5# VDD HIGH_BW# DIF_STOP PD ICS9DB403D (same as ICS9DB104) 28-pin SSOP & TSSOP Polarity Inversion Pin...