ICS9UMS9633B
Key Features
- PWR Ground pin for the REF outputs
- PWR 3.3V power for the PLL core Low threshold input for CPU frequency selection
- Refer to input electrical IN characteristics for Vil_FS and Vih_FS values
- TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode IN while in test mode
- Refer to Test Clarification Table
- TEST_SEL: latched input to select TEST MODE IN 1 = All outputs are tri-stated for test 0 = All outputs behave normally
- IN Clock pin of SMBus circuitry, 5V tolerant
- I/O Data pin for SMBus circuitry, 3.3V tolerant
- PWR 3.3V power for the PLL core PWR Power supply for low power differential outputs, nominal 1.5V
- plement clock of low power differential pair for 96.00MHz DOT clock
