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Integrated Device Technology Electronic Components Datasheet

IDT23S08T Datasheet

2.5V ZERO DELAY CLOCK MULTIPLIER

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IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
2.5V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
COMMERCIALTEMPERATURERANGE
IDT23S08T
ADVANCE
INFORMATION
FEATURES:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1/2x, 1x, 2x, 4x output options (see table):
– IDT23S08T-1 1x
– IDT23S08T-2 1x, 2x
– IDT23S08T-3 2x, 4x
– IDT23S08T-4 2x
– IDT23S08T-5 1/2x
• No external RC network required
• Operates at 2.5V VDD
• Spread spectrum compatible
• Available in SOIC package
DESCRIPTION:
The IDT23S08T is a high-speed phase-lock loop (PLL) clock multiplier. It
is designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT23S08T has two banks of four outputs each that are controlled via
twoselectaddresses.Byproperselectionofinputaddresses, both bankscan
be put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08T enters power down. In this mode, the device will
draw less than 12µA, and the outputs are tri-stated.
The IDT23S08T is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08T is characterized for Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
16
FBK
2
1
REF
2
(-5)
PLL
2
CLKA1
3
CLKA2
14
CLKA3
15
CLKA4
S2 8
S1 9
Control
Logic
(-2, -3) 2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
c 2003 Integrated Device Technology, Inc.
1
NOVEMBER 2003
DSC - 6510/4


Integrated Device Technology Electronic Components Datasheet

IDT23S08T Datasheet

2.5V ZERO DELAY CLOCK MULTIPLIER

No Preview Available !

IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
PIN CONFIGURATION
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16 FBK
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
SOIC
TOP VIEW
PIN DESCRIPTION
Pin Number Functional Description
REF (1) 1 Input Reference Clock, 3.3V Tolerant Input
CLKA1(2)
2
Clock Output for Bank A
CLKA2(2)
3
Clock Output for Bank A
VDD 4 2.5V Supply
GND 5 Ground
CLKB1(2)
6
Clock Output for Bank B
CLKB2(2)
7
Clock Output for Bank B
S2(3) 8 Select Input, Bit 2
S1(3) 9 Select Input, Bit 1
CLKB3(2)
10
Clock Output for Bank B
CLKB4(2)
11
Clock Output for Bank B
GND 12 Ground
VDD
CLKA3(2)
13
14
2.5V Supply
Clock Output for Bank A
CLKA4(2)
15
Clock Output for Bank A
FBK 16 PLL Feedback Input
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Max. Unit
VDD
Supply Voltage Range
–0.5 to +4.6 V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5 V
VI
Input Voltage Range
–0.5 to
V
(except REF)
VDD+0.5
IIK (VI < 0)
Input Clamp Current
–50 mA
IO
Continuous Output Current
±50 mA
(VO = 0 to VDD)
VDD or GND
Continuous Current
±100 mA
TA = 55°C
Maximum Power Dissipation
0.7
W
(in still air)(3)
TSTG StorageTemperatureRange –65 to +150 °C
Operating
Commercial Temperature
0 to +70 °C
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs
2


Part Number IDT23S08T
Description 2.5V ZERO DELAY CLOCK MULTIPLIER
Maker IDT
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IDT23S08T Datasheet PDF






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