IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARV AND COMMERCIAL TEMPERATURE RANGES
Four address inputs to the register file which selects one register and displays its contents through the A-port.
Four address inputs to the register file which selects one of the registers in the file, the contents of which is
displayed through the B-port. It also selects the location into which new data can be written when the clock
Nine instruction control lines which determine what data source will be applied to the ALU 10• 1• 20 what function
the ALU will perform 13. 4. 50 and what data is to be deposited in the Q Register or the register file 1.,7, ..
Four-bit direct data inputs which are the ALU data source for entering external data into the device. Do is the
Four three-state output lines which, when enabled, display either the four outputs of the ALU or the data on
the A-port of the register stack. This is determined by the destination code 1•. 7..'
Most significant ALU output bit (sign-bit).
Open drain output which goes HIGH if the Fo-F3 ALU outputs are all LOW. This indicates that the result of an
ALU operation is zero (positive logic).
Carry-in to the internal ALU.
Carry-out of the internal ALU.
Bidirectional lines controlled by 16.7..' Both are three-state output drivers connected to the TTL-compatible
CMOS inputs. When the destination code on 1.,7.. indicates an up shift, the three-state outputs are enabled
and the MSB of the Q Register is available on the Q3 pin and the MSB of the ALU output is available on the
RAM3 pin. When the destination code indicates a down shift, the pins are the data inputs to the MSB of the
Q Register and the MSB of the RAM.
Both bidirectional lines function identically to Q3 and RAM3 lines except they are the LSB of the Q Register
Output enable which, when pulled HIGH, the V outputs are OFF (high impedance). When pulled LOW, the V
outputs are enabled.
Carry generate and carry propagate output of the ALU. These are used to perform a carry-Iookahead
Overflow. This pin is logically the Exclusive-OR of the carry-in and carry-out of the MSB of the ALU. At the
most significant end of the word, this pin indicates that the result of an arithmetic two's complement operation
has overflowed into the sign-bit.
Clock input. LOW-to-HIGH clock transitions will change the Q Register and the register file outputs. Clock
LOW time is internally the write enable time for the 16x4 RAM which compromises the master latches of the
register file. While the clock is LOW, the slave latches on the RAM outputs are closed, storing the data pre-
viously on the RAM outputs. Synchronous MASTER-SLAVE operation of the register file is achieved