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IDT54AHCT573 - High Speed CMOS Octal Transparent Latch

Download the IDT54AHCT573 datasheet PDF (IDT74AHCT573 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for high speed cmos octal transparent latch.

Description

The IDT54/74AHCT573 are 8-bit latches built using advanced CEMOS'

, a dual metal CMOS technology.

This octal latch has 3-state outputs and is intended for bus-oriented applications.

The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH.

Features

  • Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes.
  • 1Ons typical data to output delay.
  • IOL = 14mA over full military temperature range.
  • CMOS power levels (5/lW typo static).
  • Both CMOS and TTL output compatible.
  • Substantially lower input current levels than ALS (5J1.A max. ).
  • Octal transparent latch with enable.
  • 100% product assurance screening to MIL-STD-883, Class B is available.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT74AHCT573-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT54AHCT573
Manufacturer IDT
File Size 191.25 KB
Description High Speed CMOS Octal Transparent Latch
Datasheet download datasheet IDT54AHCT573 Datasheet

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Full PDF Text Transcription

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FEATURES: • Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes • 1Ons typical data to output delay • IOL = 14mA over full military temperature range • CMOS power levels (5/lW typo static) • Both CMOS and TTL output compatible • Substantially lower input current levels than ALS (5J1.A max.) • Octal transparent latch with enable • 100% product assurance screening to MIL-STD-883, Class B is available • JEDEC standard pinout for DIP and LCC DESCRIPTION: The IDT54/74AHCT573 are 8-bit latches built using advanced CEMOS'·, a dual metal CMOS technology. This octal latch has 3-state outputs and is intended for bus-oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH.
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