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Integrated Device Technology Electronic Components Datasheet

IDT71T75602 Datasheet

2.5V Synchronous ZBT SRAMs

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512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71T75602
IDT71T75802
Features
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (VDDQ)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Green parts available, see Ordering Information
Functional Block Diagram - 512K x 36
LBO
Address A [0:18]
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
DQ
DQ
DQ
Clk
512Kx36 BIT
MEMORY ARRAY
Address
Control
DI DO
Control Logic
Clock
TMS
TDI
TCK
TRST
(optional)
OE
JTAG
©2017 Integrated Device Technology, Inc.
TDO
1
Mux Sel
D
Output Register
Q
Gate
Data I/O [0:31],
I/O P[1:4]
5313 drw 01
OCTOBER 2017
DSC-5313/11


Integrated Device Technology Electronic Components Datasheet

IDT71T75602 Datasheet

2.5V Synchronous ZBT SRAMs

No Preview Available !

IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Description
TheIDT71T75602/802are2.5Vhigh-speed18,874,368-bit(18 Mega-
bit) synchronous SRAMs. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes
and reads. Thus, they have been given the name ZBTTM, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read or
write.
The IDT71T75602/802 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable CEN pin allows operation of the IDT71T75602/802
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold their
previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be com-
pleted. The data bus will tri-state two cycles after the chip is deselected or
a write is initiated.
The IDT71T75602/802 have an on-chip burst counter. In the burst
mode, the IDT71T75602/802 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst
counter (ADV/LD = HIGH).
The IDT71T75602/802 SRAMs utilize a high-performance 2.5V
CMOS process, and are packaged in a JEDEC Standard 14mm x
20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid
array (BGA).
Functional Block Diagram - 1M x 18
LBO
Address A [0:19]
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
DQ
DQ
1Mx18 BIT
MEMORY ARRAY
Address
Control
DI DO
DQ
Clk
Control Logic
Clock
TMS
TDI
TCK
TRST
(optional)
OE
JTAG
TDO
6.242
Mux Sel
D
Output Register
Q
Gate
Data I/O [0:15],
I/O P[1:2]
5313 drw 01b


Part Number IDT71T75602
Description 2.5V Synchronous ZBT SRAMs
Maker IDT
Total Page 26 Pages
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