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Integrated Device Technology Electronic Components Datasheet

IDT71T75902 Datasheet

2.5V Synchronous ZBT SRAM

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1M x 18
2.5V Synchronous ZBT™ SRAM
2.5V I/O, Burst Counter
Flow-Through Outputs
IDT71T75902
Features
1M x 18 memory configuration
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW2 control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V (±5%) I/O Supply (VDDQ)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Green parts available, see Ordering Information
Functional Block Diagram — 1M x 18
LBO
Address A [0:19]
CE1, CE2 CE2
R/W
CEN
ADV/LD
BWx
DQ
DQ
1M x 18 BIT
MEMORY ARRAY
Address
Control
DI DO
DQ
Clk
Control Logic
Clock
OE
TMS
TDI
TCK
TRST
(optional)
©2017 Integrated Device Technology, Inc.
JTAG
TDO
1
Mux
Sel
Gate
Data I/O [0:15], I/O P[1:2]
5319 drw 01a
SEPTEMBER 2017
DSC-5319/10


Integrated Device Technology Electronic Components Datasheet

IDT71T75902 Datasheet

2.5V Synchronous ZBT SRAM

No Preview Available !

IDT71T75902 1M x 18, 2.5V Synchronous ZBT™ SRAM with
2.5V I/O, Burst Counter and Flow-Through Outputs
Description
The IDT71T75902 is a 2.5V high-speed 18,874,368-bit (18 Megabit)
synchronous SRAM organized as 1M x 18. It is designed to eliminate
dead bus cycles when turning the bus around between reads and writes,
orwritesandreads.Thusithas beengiventhenameZBTTM, or Zero Bus
Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and on the next clock cycle the associated data cycle occurs,
be it read or write.
The IDT71T75902 contain address, data-in and control signal regis-
ters. The outputs are flow-through (no output data register). Output enable
is the only asynchronous signal and can be used to disable the outputs
at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71T75902 to be
suspended as long as necessary. All synchronous inputs are
ignored when CEN is high and the internal device registers will hold their
previous values.
Commercial and Industrial Temperature Ranges
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71T75902 has an on-chip burst counter. In the burst mode,
the IDT71T75902 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. TheLBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71T75902 SRAM utilize IDT’s high-performance CMOS
process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
Pin Description Summary
A0-A19
Address Inputs
CE1, CE2, CE2
Chip Enables
OE Output Enable
R/W Read/Write Signal
CEN Clock Enable
BW1, BW2
Individual Byte Write Selects
CLK Clock
ADV/LD
Advance Burst Address/Load New Address
LBO Linear/Interleaved Burst Order
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock
TDO Test Data Output
TRST
JTAG Reset (Optional)
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP2
Data Input/Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Synchronous
Static
Static
5319 tbl 01a
6.422


Part Number IDT71T75902
Description 2.5V Synchronous ZBT SRAM
Maker IDT
Total Page 23 Pages
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