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IDT71V2556XSA - 3.3V Synchronous ZBT SRAMs

This page provides the datasheet information for the IDT71V2556XSA, a member of the IDT71V2556S 3.3V Synchronous ZBT SRAMs family.

Description

The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5

Features

  • 128K x 36 memory configurations.
  • Supports high performance system speed - 166 MHz (3.5 ns Clock-to-Data Access).
  • ZBTTM Feature - No dead cycles between write and read cycles.
  • Internally synchronized output buffer enable eliminates the need to control OE.
  • Single R/W (READ/WRITE) control pin.
  • Positive clock-edge triggered address, data, and control signal registers for fully pipelined.

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Datasheet preview – IDT71V2556XSA

Datasheet Details

Part number IDT71V2556XSA
Manufacturer IDT
File Size 302.55 KB
Description 3.3V Synchronous ZBT SRAMs
Datasheet download datasheet IDT71V2556XSA Datasheet
Additional preview pages of the IDT71V2556XSA datasheet.

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Full PDF Text Transcription

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128K x 36 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs IDT71V2556S/XS IDT71V2556SA/XSA Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 166 MHz (3.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRITE) control pin ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ 4-word burst capability (interleaved or linear) ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ Three chip enables for simple depth expansion ◆ 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ) ◆ Optional - Boundary Scan JTAG Interface (IEEE 1149.
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