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Integrated Device Technology Electronic Components Datasheet

IDT71V424S Datasheet

3.3V CMOS Static RAM

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3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
IDT71V424S
IDT71V424L
Features
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
Functional Block Diagram
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using high-perfomance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
A0
A18
ADDRESS
DECODER
4,194,304-BIT
MEMORY ARRAY
I/O0 - I/O7
WE
OE
CS
8
8
CONTROL
LOGIC
I/O CONTROL
8
3622 drw 01
©2013 Integrated Device Technology, Inc.
1
SEPTEMBER 2013
DSC-3622/10


Integrated Device Technology Electronic Components Datasheet

IDT71V424S Datasheet

3.3V CMOS Static RAM

No Preview Available !

IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Pin Configuration
A0
A1
A2
A3
A4
CS
I/O 0
I/O 1
VDD
VSS
I/O 2
I/O 3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9 SO36-1
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O 7
I/O 6
VSS
VDD
I/O 5
I/O 4
A14
A13
A12
A11
A10
NC
SOJ
3622 drw 02
Top View
Commercial and Industrial Temperature Ranges
Pin Configuration
NC
NC
A0
A1
A2
A3
A4
CS
I/00
I/01
V DD
V SS
I/02
I/03
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-2
44 NC
43 NC
42 NC
41 A18
40 A17
39 A16
38 A15
37 OE
36 I/07
35 I/06
34 V SS
33 V DD
32 I/05
31 I/04
30 A14
29 A13
28 A12
27 A11
26 A10
25 NC
24 NC
23 NC
Pin Description
A0 – A18
Address Inputs
CS Chip Select
WE Write Enable
OE Output Enable
I/O0 - I/O7
Data Input/Output
VDD 3.3V Power
VSS Ground
TSOP
Top View
3622 drw 11
Input
Input
Input
Input
I/O
Power
Gnd
3622 tbl 02
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol
Parameter(1)
Conditions Max. Unit
CIN Input Capacitance
VIN = 3dV
7 pF
CI/O I/O Capacitance
VOUT = 3dV
8 pF
NOTE:
3622 tbl 03
1. This parameter is guaranteed by device characterization, but not production
tested.
Truth Table(1,2)
CS OE WE
I/O
Function
L L H DATAOUT Read Data
L X L DATAIN Write Data
L H H High-Z Output Disabled
H X X High-Z Deselected - Standby (ISB)
VHC(3)
X
X High-Z Deselected - Standby (ISB1)
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VDD -0.2V.
3. Other inputs VHC or VLC.
3622 tbl 01
6.242


Part Number IDT71V424S
Description 3.3V CMOS Static RAM
Maker IDT
Total Page 9 Pages
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