256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
x 256K x 36, 512K x 18 memory configurations
x Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x 4-word burst capability (Interleaved or linear)
x Individual byte write (BW1-BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 3.3V power supply (±5%)
x 2.5V (±5%) I/O Supply (VDDQ)
x Power down controlled by ZZ input
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x
18. They are designed to eliminate dead bus cycles when turning the
bus around between reads and writes, or writes and reads. Thus they
have been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and on the next clock cycle the associated data cycle
occurs, be it read or write.
The IDT71V65702/5902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V65702/5902
to be suspended as long as necessary. All synchronous inputs are ignored
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
The IDT71V65702/5902 have an on-chip burst counter. In the burst
mode, the IDT71V65702/5902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V65702/5902 SRAMs utilize IDT’s latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Pin Description Summary
CE1, CE2, CE2
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Advance Burst Address/Load New Address
LBO Linear/Interleaved Burst Order
ZZ Sleep Mode
Core Power, I/O Power
Sup p ly
Sup p ly
5315 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
©2004 Integrated Device Technology, Inc.