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Integrated Device Technology Electronic Components Datasheet

IDT71V65702 Datasheet

(IDT71V65702 / IDT71V65902) Synchronous ZBT SRAMs

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256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
IDT71V65702
IDT71V65902
Features
x 256K x 36, 512K x 18 memory configurations
x Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
cycles
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x 4-word burst capability (Interleaved or linear)
x Individual byte write (BW1-BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 3.3V power supply (±5%)
x 2.5V (±5%) I/O Supply (VDDQ)
x Power down controlled by ZZ input
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x
18. They are designed to eliminate dead bus cycles when turning the
bus around between reads and writes, or writes and reads. Thus they
have been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and on the next clock cycle the associated data cycle
occurs, be it read or write.
The IDT71V65702/5902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V65702/5902
to be suspended as long as necessary. All synchronous inputs are ignored
when CENishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71V65702/5902 have an on-chip burst counter. In the burst
mode, the IDT71V65702/5902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V65702/5902 SRAMs utilize IDT’s latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
CE1, CE2, CE2
OE
R/W
Chip Enables
Output Enable
Read/Write Signal
CEN
BW1, BW2, BW3, BW4
Clock Enable
Individual Byte Write Selects
CLK Clock
ADV/LD
Advance Burst Address/Load New Address
LBO Linear/Interleaved Burst Order
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input/Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
I/ O
Sup p ly
Sup p ly
Synchro nous
Synchro nous
Asynchro nous
Synchro nous
Synchro nous
Synchro nous
N/A
Synchro nous
Static
Asynchro nous
Synchro nous
Static
Static
5315 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
©2004 Integrated Device Technology, Inc.
1
OCTOBER 2004
DSC-5315/08


Integrated Device Technology Electronic Components Datasheet

IDT71V65702 Datasheet

(IDT71V65702 / IDT71V65902) Synchronous ZBT SRAMs

No Preview Available !

IDT71V65702 pdf
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Range
Pin Definitions(1)
Symbol Pin Function I/O Active
Description
A0-A18 Address Inputs I N/A Synchro nous Address inputs. The address register is triggered by a co mbination of the rising edge of
CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/ LD is low with
the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the
internal burst counter is advanced for any burst that was in progress. The external addresses are
ignored when ADV/LD is sampled high.
R/W
Read / Write
I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the current cycle takes place one clock
cycle later.
CEN
Clock Enable
I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be
sampled low at rising edge of clock.
BW1-BW4 Individual Byte
Write Enables
I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load
write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4)
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write
signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the
device one cycle later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word.
CE1, CE2 Chip Enables
I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V65702/5902
(CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates
a deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data b us will tri-state one clock cycle
after deselect is initiated.
CE2
Chip Enable
I HIGH Synchrono us active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has
inverted po larity but otherwise identical to CE1 and CE2.
CLK
Clock
I N/A This is the clock input to the IDT71V65702/5902. Except for OE, all timing references for the device are
made with respect to the rising edge of CLK.
I/O0-I/O31 Data Input/Output I/O N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
I/OP1-I/OP4
data output path is flow-through (no output register).
LBO
Linear Burst
I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO
Order
is low the Linear burst sequence is selected. LBO is a static input, and it must not change during
device operation.
OE Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V65702/5902. When OE is HIGH
the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and
write cycles. In normal operation, OE can be tied low.
ZZ
Sleep Mode
I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V65702/5902 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
VDD Power Supply N/A N/A 3.3V core power supply.
VDDQ Power Supply N/A N/A 2.5V I/O supply.
VSS
Ground
N/A N/A Ground.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
5315 tbl 02
6.422


Part Number IDT71V65702
Description (IDT71V65702 / IDT71V65902) Synchronous ZBT SRAMs
Maker IDT
Total Page 26 Pages
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