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Integrated Device Technology Electronic Components Datasheet

IDT72615 Datasheet

CMOS SyncBiFIFO

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CMOS SyncBiFIFOTM
256 x 18 x 2
512 x 18 x 2
IDT72605
IDT72615
FEATURES:
Two independent FIFO memories for fully bidirectional data
transfers
256 x 18 x 2 organization (IDT72605)
512 x 18 x 2 organization (IDT72615)
Synchronous interface for fast (20ns) read and write cycle times
Each data port has an independent clock and read/write control
Output enable is provided on each port as a three-state control
of the data bus
Built-in bypass path for direct data transfer between two ports
Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO
Programmable flag offset can be set to any depth in the FIFO
The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin
Quad Flatpack) and 68-pin PLCC
Industrial temperature range (–40°C to +85°C)
Green parts available, see ordering information
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-power bidirec-
tional First-In, First-Out (FIFO) memories, with synchronous interface for fast
read and write cycle times. The SyncBiFIFO™ is a data buffer that can store
or retrieve information from two sources simultaneously. Two Dual-Port FIFO
memory arrays are contained in the SyncBiFIFO; one data buffer for each
direction.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Each Port has its own independent clock. Data transfers to the
I/O registers are gated by the enable signals. The transfer direction for each
portiscontrolledindependentlybyaread/writesignal. Individualoutputenable
signals control whether the SyncBiFIFO is driving the data lines of a port or
whether those data lines are in a high-impedance state.
Bypass control allows data to be directly transferred from input to output
register in either direction.
The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full,
and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full
and Almost-Empty flags can be programmed to any location.
The SyncBiFIFO is fabricated using high-speed, submicron CMOS tech-
nology.
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
ENA
R/WA
OEA
HIGH
Z
CONTROL
CSA
A2
A1
A0
EFAB
PAEAB
PAFAB
FFAB
CLKA
μP
INTERFACE
FLAG
LOGIC
INPUT REGISTER
MEMORY
ARRAY
512 x 18
256 x 18
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
CLKB
MUX
OUTPUT REGISTER
INPUT REGISTER
OEB
R/WB
ENB
HIGH
Z
CONTROL
BYPB
DB0-DB17
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RESET
LOGIC
FLAG
LOGIC
POWER
SUPPLY
RS
EFBA
PAEBA
PAFBA
FFBA
3 VCC
7 GND
2704 drw 01
FEBRUARY 2013
DSC-2704/10


Integrated Device Technology Electronic Components Datasheet

IDT72615 Datasheet

CMOS SyncBiFIFO

No Preview Available !

IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
PIN CONFIGURATIONS
INDUSTRIALTEMPERATURERANGE
DA16
CA17
CLKA
R/WA
ENA
CSA
A0
A1
A2
VCC
EFAB
FFAB
PAEAB
PAFAB
OEA
DB17
DB16
9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61
10 1 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DA2
DA1
DA0
EFBA
FFBA
PAEBA
PAFBA
GND
BYPB
OEB
ENB
R/WB
CLKB
RS
DB0
DB1
DB2
PLCC (J68-1, order code: J)
TOP VIEW
2704 drw 02
PIN 1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
GND
VCC
DA10
DA11
DA12
DA13
DA14
DA15
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DB3
DB4
GND
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
GND
DB15
DB16
TQFP (PN64-1, order code: PF)
TOP VIEW
2
2704 drw 03


Part Number IDT72615
Description CMOS SyncBiFIFO
Maker IDT
Total Page 17 Pages
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