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Integrated Device Technology Electronic Components Datasheet

IDT728985 Datasheet

TIME SLOT INTERCHANGE DIGITAL SWITCH

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TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
IDT728985
.EATURES:
256 x 256 channel non-blocking switch
Automatic signal identification (ST-BUS®, GCI)
8 RX inputs — 32 channels at 64 Kbit/s per serial line
8 TX outputs — 32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
Frame Integrity for data applications
5V Power Supply
Operating Temperature Range -40°C to +85°C
Available in 44-pin Plastic Leaded Chip Carrier (PLCC),
44-pin Plastic Quad Flatpack (PQFP) and 40-pin Plastic Dip
(P-DIP)
DESCRIPTION:
The IDT728985 is a ST-BUS®/GCI compatible digital switch controlled by
amicroprocessor. TheIDT728985canhandleasmanyas256,64Kbit/sinput
and output channels. Those 256 channels are divided into 8 serial inputs and
outputs,eachofwhichconsistsof32channels. TheIDT728985providesper-
channel variable or constant throughput delay modes and microprocessor read
and write access to individual channels. As an important function of a digital
switch is to maintain sequence integrity and minimize throughput delay, the
IDT728985 is an ideal solution for most switching needs.
.UNCTIONAL DESCRIPTION
Frame sequence, constant throughput delay, and guaranteed minimum
delay are high priority requirements in today’s integrated data and multimedia
networks. The IDT728985 provides these functions on a per-channel basis
usingastandardmicroprocessorcontrolinterface. Eachoftheeightseriallines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
In Processor Mode, the microprocessor can access the input and output time
slots to control other devices such as ISDN transceivers and trunk interfaces.
Supporting both GCI and ST-BUS® formats, IDT728985 has incorporated an
internal circuit to automatically identify the polarity and format of the frame
synchronization.
A functional block diagram of the IDT728985 device is shown on page 1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µswideframeseachcontaining32,8-bitchannels. Eightinput(RX0-7)and
.UNCTIONAL BLOCK DIAGRAM
C4i F0i VCC GND
ODE
RX0 Timing
Unit Output MUX
RX1
RX2
Receive
RX3 Serial Data
Data
RX4 Streams Memory
Transmit
Serial Data
Streams
RX5
Control Register
Connection
RX6 Memory
RX7 Microprocessor Interface
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
DS CS R/W A0/ DTA D0/
A5 D7
CCO
5708 drw01
2001 Integrated Device Technology, Inc.
1
APRIL 2001
DSC-5708/2


Integrated Device Technology Electronic Components Datasheet

IDT728985 Datasheet

TIME SLOT INTERCHANGE DIGITAL SWITCH

No Preview Available !

IDT728985 Time Slot Interchange
Digital Switch 256 x 256
PIN CON.IGURATION
Commercial Temperature Range
INDEX
INDEX
RX3
RX4
RX5
RX6
RX7
VCC
F0i
C4i
A0
A1
A2
7
8
9
10
11
12
13
14
15
16
17
39 TX3
38 TX4
37 TX5
36 TX6
35 TX7
34 GND
33 D0
32 D1
31 D2
30 D3
29 D4
5708 drw02
PLCC: 0.05in. pitch, 0.65in. x 0.65in.
(J44-1, order code: J)
TOP VIEW
NOTE:
1. DNC - Do Not Connect
DTA
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
VCC
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 CCO
39 ODE
38 TX0
37 TX1
36 TX2
35 TX3
34 TX4
33 TX5
32 TX6
31 TX7
30 GND
29 D0
28 D1
27 D2
26 D3
25 D4
24 D5
23 D6
22 D7
21 CS
5708 drw04
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in.
(P40-1, order code: P)
TOP VIEW
RX3
RX4
RX5
RX6
RX7
VCC
F0i
C4i
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
33 TX3
32 TX4
31 TX5
30 TX6
29 TX7
28 GND
27 D0
26 D1
25 D2
24 D3
23 D4
5708 drw03
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
PIN DESCRIPTIONS
SYMBOL
NAME
I/O
DESCRIPTION
GND
VCC
DTA
RX0-7
F0i
C4i
A0-A5
DS
R/W
CS
D0-D7
TX0-7
ODE
CCO
Ground.
Ground Rail.
VCC +5.0 Volt Power Supply.
Data Acknowledgment O This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
(Open Drain)
output.
RX Input 0 to 7
I Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
Frame Pulse
I This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS® and GCI.
Clock
I 4.096 MHz serial clock for shifting data in and out of the data streams.
Address 0 to 5
I These lines provide the address to IDT728985 internal registers.
Data Strobe
I This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS to enable the internal read and write generation.
Read/Write
I This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Chip Select
I Active LOW input enabling a microprocessor read or write of control register or internal memories.
Data Bus 0 to 7
I/O These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
TX Outputs 0 to 7
(Three-state Outputs)
O Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
Output Drive Enable
I This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
Control Channel Output O This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the
contents of the CCO bit in the Connection Memory HIGH locations.
2


Part Number IDT728985
Description TIME SLOT INTERCHANGE DIGITAL SWITCH
Maker IDT
Total Page 13 Pages
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