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IDT72T36135M - FIFO 36-BIT CONFIGURATIONS

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IDT

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IDT72T36135M FIFO 36-BIT CONFIGURATIONS by IDT - Datasheet Preview — Datasheet preview – IDT72T36135M

Datasheet Details

Part number	IDT72T36135M
Manufacturer	IDT
File Size	495.32 KB
Description	FIFO 36-BIT CONFIGURATIONS
Datasheet	IDT72T36135M Datasheet
Additional preview pages of the IDT72T36135M datasheet.

Product details

Features

Industry’s largest FIFO memory organization: IDT72T36135 ⎯ 524,288 x 36 - 18M-bits.
Up to 200 MHz Operation of Clocks.
Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync devices.
User selectable HSTL/LVTTL Input and/or Output.
User selectable Asynchronous read and/or write port timing.
Mark & Retransmit, resets read pointer to user marked position.
Write Chip Select (WCS) input disables Write Port.
Read Chip Sel.

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Published: Apr 6, 2019 |