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Integrated Device Technology Electronic Components Datasheet

IDT72T36135M Datasheet

FIFO 36-BIT CONFIGURATIONS

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2.5V 18M-BIT HIGH-SPEED TeraSyncTM
FIFO 36-BIT CONFIGURATIONS
524,288 x 36
IDT72T36135M
FEATURES:
Industry’s largest FIFO memory organization:
IDT72T36135 524,288 x 36 - 18M-bits
Up to 200 MHz Operation of Clocks
Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync
devices
User selectable HSTL/LVTTL Input and/or Output
User selectable Asynchronous read and/or write port timing
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input disables Write Port
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty and Full flags signal FIFO status
Select IDT Standard timing (using EF[1:2] and FF[1:2] flags) or First
Word Fall Through timing (using OR[1:2] and IR[1:2] flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
50% more space saving than the leading 9M-bit FIFOs
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK/WR
WCS
D0 -Dn (x36)
INPUT REGISTER
ASYW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
Vref
WHSTL
RHSTL
SHSTL
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
JTAG CONTROL
(BOUNDARY
SCAN)
HSTL I/0
CONTROL
RAM ARRAY
524,288 x 36
OUTPUT REGISTER
OE
Q0 -Qn (x36)
LD SEN SCLK
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR[1:2]
PAF[1:2]
EF/OR[1:2]
PAE[1:2]
FWFT/SI
PFM
FSEL0
FSEL1
READ
CONTROL
LOGIC
RT
MARK
ASYR
RCLK/RD
REN
RCS
6723 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2016
DSC-6723/5


Integrated Device Technology Electronic Components Datasheet

IDT72T36135M Datasheet

FIFO 36-BIT CONFIGURATIONS

No Preview Available !

IDT72T36135M 2.5V 18M-BIT TeraSync36-BIT FIFO
524,288 x 36
PIN CONFIGURATION
A1 BALL PAD CORNER
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A
VCC VCC VCC VCC VCC VCC WCLK PRS GND FF1 FF2 RCLK OE VDDQ VDDQ VDDQ VDDQ VDDQ
B
VCC
VCC
VCC
VCC
VCC
VCC WEN MRS GND
PAF1 EF1
REN RCS VDDQ VDDQ VDDQ VDDQ VDDQ
C
VCC
VCC VCC
VCC VCC VCC WCS LD
GND
PAF2 PAE1 MARK RT
VDDQ VDDQ VDDQ VDDQ VDDQ
D
VCC VCC VCC FWFT/SI DNC FSEL0 SHSTL FSEL1 GND GND PAE2 EF2 RHSTL ASYR PFM VDDQ VDDQ VDDQ
E
VCC VCC VCC GND
GND VDDQ VDDQ VDDQ
F
VCC VCC VCC GND
GND VDDQ VDDQ VDDQ
G
VCC SEN SCLK WHSTL
GND VDDQ VDDQ VDDQ
H
VCC VCC VCC ASYW
J
VCC VCC VCC VREF
K
VCC VCC VCC DNC
L
D33 D34 D35 GND
M
D30 D31 D32 GND
GND GND GND GND
GND GND GND GND
GND GND GND GND
GND GND GND GND
GND VDDQ VDDQ VDDQ
GND VDDQ VDDQ VDDQ
GND VDDQ VDDQ VDDQ
GND VDDQ Q35 Q34
GND Q33 Q32 Q31
N
D27 D28 D29 GND
GND Q30 Q29 Q28
P
D24 D25 D26 GND
GND Q27 Q26 Q25
R
D21 D22 D23 GND GND GND GND GND GND GND GND GND GND GND GND Q24 Q23 Q22
T
D19 D20 D13 D10
D5
D4
D1 TMS TDO GND Q0
Q2
Q3
Q8 Q11 Q14 Q21 Q20
U
D18 D17 D14 D11 D7 D8 D2 TRST TDI GND Q1 Q6 Q5 Q9 Q12 Q15 Q18 Q19
V
VCC D16 D15 D12
D9
D6
D3 D0 TCK GND DNC Q4
Q7 Q10 Q13 Q16 Q17 VDDQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
NOTE:
1. DNC - Do Not Connect.
6723 drw02
PBGA: 1mm pitch, 19mm x 19mm (BB240, order code: BB)
TOP VIEW
2


Part Number IDT72T36135M
Description FIFO 36-BIT CONFIGURATIONS
Maker IDT
Total Page 30 Pages
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