IDT72T51253 Datasheet | IDT

FEATURES : - - - - - - - - - - - Choose from among the following memory density options: IDT72T51233  Total Available Memory = 589,824 bits IDT72T51243  Total Available Memory = 1,179,648 bits IDT72T51253  Total Available Memory = 2,359,296 bits Configurable from 1 to 4 Queues Queues may be configured at master reset from the pool of Total Available Memory in blocks of 512 x 18 or 1,024 x 9 Independent Read and Write access per queue User programmable via serial port User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V e HSTL Default multi-queue device configurations -IDT72T51233: 8,192 x 18 x 4Q -IDT72T51243: 16,384 x 18 x 4Q -IDT72T51253: 32,768 x 18 x 4Q 100% Bus Utilization, Read and Write on every clock cycle 200 MHz High speed operation (5ns cycle time) 3.6ns access time Echo Read Enable & Echo Read Clock Outputs - - - - - - - - - - - - - Individual, Active queue flags (OV, FF, PAE, PAF) 4 bit parallel flag status on both read and write ports Provides continuous PAE and PAF status of up to 4 Queues Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width) User Selectable Bus Matching Options: - x18in to x18out - x9in to x18out - x18in to x9out - x9in to x9out FWFT mode of operation on read port Partial Reset, clears data in single Queue Expansion of up to 8 multi-queue devices in parallel is available Power Down Input provides additional power savings in HSTL and e HSTL modes. JTAG Functionality (Boundary Scan) Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm HIGH Performance submicron CMOS technology Industrial temperature range (-40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MULTI-QUEUE FLOW-CONTROL DEVICE WADEN FSTR WRADD WEN WCLK READ CONTROL RADEN ESTR RDADD WRITE CONTROL Q0 REN RCLK EREN ERCLK OE x9, x18 DATA IN FF PAF PAFn Din Qout x9, x18 DATA OUT READ FLAGS OV PAE PAEn WRITE...