Description
The IDT72T51233/72T51243/72T51253 multi-queue flow-control devices are single chip within which anywhere between 1 and 4 discrete FIFO queues can be setup.
All queues within the device have a common data input bus, (write port) and a common data output bus, (read port).
Features
- Choose from among the following memory density options: IDT72T51233 Total Available Memory = 589,824 bits IDT72T51243 Total Available Memory = 1,179,648 bits IDT72T51253 Total Available Memory = 2,359,296 bits Configurable from 1 to 4 Queues Queues may be configured at master reset from the pool of Total Available Memory in blocks of 512 x 18 or 1,024 x 9 Independent Read and W.