IDT72T51546 - (IDT72T51546 / IDT72T51556) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES

Description

The IDT72T51546/72T51556 multi-queue flow-control devices is a single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup.

All queues within the device have a common data input bus, (write port) and a common data output bus, (read port).

Features

• Choose from among the following memory density options: IDT72T51546  Total Available Memory = 1,179,648 bits IDT72T51556  Total Available Memory = 2,359,296 bits Configurable from 1 to 32 Queues Queues may be configured at master reset from the pool of Total Available Memory in blocks of 256 x 36 Independent Read and Write access per queue User program.