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IDT72T51546 Datasheet

(IDT72T51546 / IDT72T51556) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES

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ADVANCE INFORMATION
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION
1,179,648 bits and 2,359,296 bits
IDT72T51546
IDT72T51556
FEATURES:
Choose from among the following memory density options:
IDT72T51546 Total Available Memory = 1,179,648 bits
IDT72T51556 Total Available Memory = 2,359,296 bits
Configurable from 1 to 32 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
Independent Read and Write access per queue
User programmable via serial port
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
Default multi-queue device configurations
– IDT72T51546 : 1,024 x 36 x 32Q
– IDT72T51556 : 2,048 x 36 x 32Q
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV, FF, PAE, PAF, PR)
8 bit parallel flag status on both read and write ports
Shows PAE and PAF status of 8 Queues
FUNCTIONAL BLOCK DIAGRAM
Direct or polled operation of flag status bus
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
– x36in to x36out
– x18in to x36out
– x9in to x36out
– x36in to x18out
– x36in to x9out
FWFT mode of operation on read port
Packet mode operation
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
MULTI-QUEUE FLOW-CONTROL DEVICE
WADEN
FSTR
WRADD
8
WEN
WCLK
Din
x36
DATA IN
FF
PAF
PAFn
8
Q0
Q1
Q2
Q31
RADEN
ESTR
RDADD
8 REN
RCLK
EREN
ERCLK
OE
Qout
x36
DATA OUT
OV
PR
PAE
PAEn
8 PRn
5998 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-5998/3


Integrated Device Technology Electronic Components Datasheet

IDT72T51546 Datasheet

(IDT72T51546 / IDT72T51556) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES

No Preview Available !

IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
DESCRIPTION:
The IDT72T51546/72T51556 multi-queue flow-control devices is a single
chip within which anywhere between 1 and 32 discrete FIFO queues can be
setup. All queues within the device have a common data input bus, (write port)
and a common data output bus, (read port). Data written into the write port is
directed to a respective queue via an internal de-multiplex operation, ad-
dressed by the user. Data read from the read port is accessed from a respective
queue via an internal multiplex operation, addressed by the user. Data writes
and reads can be performed at high speeds up to 200MHz, with access times
of 3.6ns. Data write and read operations are totally independent of each other,
a queue maybe selected on the write port and a different queue on the read
port or both ports may select the same queue simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 8 bit programmable flag busses are available, providing status of queues
not selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when
more than 8 queues are used, either a Polled or Direct mode of bus operation
provides the flag busses with all queues status.
Bus Matching is available on this device, either port can be 9 bits, 18 bits
or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching
is used the device ensures the logical transfer of data throughput in a Little
Endian manner.
A packet mode of operation is also provided when the device is configured
for 36 bit input and 36 bit output port sizes. The Packet mode provides the user
with a flag output indicating when at least one (or more) packets of data within
a queue is available for reading. The Packet Ready provides the user with
a means by which to mark the start and end of packets of data being passed
through the queues. The multi-queue device then provides the user with an
internally generated packet ready status per queue.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 32, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins are provided on this device. A Master
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual queue, provided that the queue is selected on both
the write port and read port at the time of partial reset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the Queue that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect toERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
speed.
The multi-queue flow-control device has the capability of operating its IO in
either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected
via the IOSEL input. The core supply voltage (VCC) to the multi-queue is always
2.5V, however the output levels can be set independently via a separate supply,
VDDQ.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
required.
A JTAG test port is provided, here the multi-queue flow-control device has a
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline
of the functional blocks within the device.
2


Part Number IDT72T51546
Description (IDT72T51546 / IDT72T51556) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
Maker IDT
Total Page 30 Pages
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