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Integrated Device Technology Electronic Components Datasheet

IDT72T7295 Datasheet

FIFO 72-BIT CONFIGURATIONS

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2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
16,384 x 72, 32,768 x 72,
65,536 x 72, 131,072 x 72
IDT72T7285, IDT72T7295,
IDT72T72105, IDT72T72115
FEATURES:
Choose among the following memory organizations:
IDT72T7285 16,384 x 72
IDT72T7295 32,768 x 72
IDT72T72105 65,536 x 72
IDT72T72115 131,072 x 72
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input disables Write Port HSTL inputs
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts are available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK/WR
WCS
D0 -Dn (x72, x36 or x18)
LD SEN SCLK
INPUT REGISTER
OFFSET REGISTER
ASYW
BE
IP
WRITE CONTROL
LOGIC
WRITE POINTER
CONTROL
LOGIC
RAM ARRAY
16,384 x 72
32,768 x 72
65,536 x 72
131,072 x 72
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
BM
IW
OW
MRS
PRS
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
MARK
ASYR
TCK
TRST
TMS
TDO
TDI
Vref
WHSTL
RHSTL
SHSTL
JTAG CONTROL
(BOUNDARY SCAN)
HSTL I/0
CONTROL
OE
Q0 -Qn (x72, x36 or x18)
EREN
ERCLK
RCLK/RD
REN
RCS
5994 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
JUNE 2017
DSC-5994/16


Integrated Device Technology Electronic Components Datasheet

IDT72T7295 Datasheet

FIFO 72-BIT CONFIGURATIONS

No Preview Available !

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
PIN CONFIGURATION
A1 BALL PAD CORNER
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A
VCC D60 D61 D63 D66 D69 WCLK PRS GND FF EREN RCLK OE Q69 Q66 Q64 Q63 VDDQ
B
D59 D58
D62 D64 D67
D70 WEN MRS GND PAF
EF REN RCS Q70 Q67 Q65
Q61 Q62
C
D57 D56 D55 D65 D68 D71 WCS
LD GND HF
PAE MARK RT
Q71 Q68 Q58 Q59 Q60
D
D54 D53 D52 FWFT/SI OW FS0 SHSTL FS1 GND BE
IP BM RHSTL ASYR PFM Q55 Q56 Q57
E
D51 D50 D49 VCC VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q52 Q53 Q54
F
D48 D47 D46 VCC VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q49 Q50 Q51
G
D45 SEN SCLK WHSTL VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q46
Q47 Q48
H
D44 D43 D42 ASYW VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q43 Q44 Q45
J
D41 D40 D39 VREF VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q40 Q41 Q42
K
D36 D37 D38 IW VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q39 Q38 Q37
L
D33 D34
D35 VCC VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q36
Q35 Q34
M
D30 D31 D32 VCC VCC VCC GND GND GND GND GND GND VDDQ VDDQ VDDQ Q33 Q32 Q31
N
D27 D28 D29 VCC
VCC VCC
VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q30
Q29 Q28
P
D24 D25 D26 VCC
VCC VCC
VCC VCC
GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q27
Q26 Q25
R
D21 D22 D23 VCC VCC VCC VCC VCC GND GND VDDQ VDDQ VDDQ VDDQ VDDQ Q24 Q23 Q22
T
D19 D20 D13 D10 D5 D4 D1 TMS TDO GND Q0 Q2 Q3 Q8 Q11 Q14 Q21 Q20
U
D18 D17 D14 D11 D7
D8 D2 TRST TDI GND Q1 Q6 Q5 Q9 Q12 Q15 Q18 Q19
V
VCC D16 D15 D12
D9
D6
D3 D0 TCK GND ERCLK Q4 Q7 Q10 Q13 Q16 Q17 VDDQ
12
34
56
78
9 10 11 12 13 14 15 16 17 18
5994 drw02
PBGA: 1mm pitch, 19mm x 19mm (BB324, BBG324) Order code: BB, BBG
TOP VIEW
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Part Number IDT72T7295
Description FIFO 72-BIT CONFIGURATIONS
Maker IDT
Total Page 30 Pages
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