1-to-5 differential-to-3.3v lvpecl fanout buffer.
* Five differential 3.3V LVPECL outputs
* Selectable differential CLK, xCLK, or LVPECL clock inputs
* CLK, xCLK pair can accept the following differential in.
that demand well-defined performance and repeatability.
FUNCTIONAL BLOCK DIAGRAM
CLK_EN
D Q
CLK xCLK PCLK xPCLK 1 0
.
The IDT85304-01 is a low skew, high performance 1-to-5 differential-to3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The CLK/ xCLK pair can accept most standard differential input levels. The PCLK/ xPCLK pair can accept LV.
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