900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Integrated Device Technology Electronic Components Datasheet

STAC9753 Datasheet

(STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS

No Preview Available !

www.DataSheet4U.com
DATASHEET
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE STAC9752/9753
DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
Description
IDT's STAC9752/9753 are general purpose 20-bit, full
duplex, audio CODECs conforming to the analog
component specification of AC'97 (Audio CODEC 97
Component Specification Rev. 2.3). The STAC9752/9753
incorporate IDT's proprietary Σ∆ technology to achieve a
DAC SNR in excess of 90dB. The DACs, ADCs and mixer
are integrated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs,
two stereo outputs, and one mono output channel. The
STAC9752/9753 include digital output capability for support
of modern PC systems with an output that supports the
SPDIF format. The STAC9752/9753 are standard
2-channel stereo CODECs. With IDT’s headphone
capability, headphones can be driven without an external
amplifier. The STAC9752/9753 may be used as a
secondary or tertiary CODECs, with STAC9700/21/44/56/
08/84/50/66 as the primary, in a multiple CODEC
configuration conforming to the AC'97 Rev. 2.3
specification. This configuration can provide the true
six-channel, AC-3 playback required for DVD applications.
The STAC9752/9753 communicate via the five AC-Link
lines to any digital component of AC'97, providing flexibility
in the audio system design. Packaged in an AC'97
compliant 48-pin TQFP, the STAC9752/9753 can be placed
on the motherboard, daughter boards, PCI, AMR, CNR,
MDC or ACR cards.
Features
High performance Σ∆ technology
AC’97 Rev 2.3 compliant
20-bit full duplex stereo ADCs, DACs
Independent sample rates for ADCs & DACs
5-wire AC-Link protocol compliance
20-bit SPDIF Output
Internal Jack Sensing on Headphone and Line_Out
Internal Microphone Input Sensing
Digital PC Beep Option
Extended AC’97 2.3 Paging Registers
Adjustable VREF amplifier
Digital-ready status
General purpose I/Os
Crystal Elimination Circuit
Headphone drive capability (50 mW)
0dB, 10dB, 20dB, and 30dB microphone boost
capability
+3.3 V (STAC9753) and +5 V (STAC9752) analog
power supply options
Pin compatible with the STAC9700, STAC9721,
STAC9756
100% pin compatible with STAC9750 and
STAC9766
IDT Surround (SS3D) Stereo Enhancement
Energy saving dynamic power modes
Multi-CODEC option (Intel AC'97 rev 2.3)
Six analog line-level inputs
90dB SNR Line to Line
SNR > 89dB through Mixer and DAC
IDT™
1 STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
V 3.3 101006


Integrated Device Technology Electronic Components Datasheet

STAC9753 Datasheet

(STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS

No Preview Available !

STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
TABLE OF CONTENTS
1. PRODUCT BRIEF ...................................................................................................................... 7
1.1. Description ........................................................................................................................................ 7
1.2. STAC9752/9753 Block Diagram ........................................................................................................ 8
1.3. Key Specifications ............................................................................................................................. 8
1.4. Related Materials .............................................................................................................................. 9
1.5. Additional Support ............................................................................................................................. 9
2. CHARACTERISTICS AND SPECIFICATIONS .......................................................................10
2.1. Electrical Specifications ................................................................................................................... 10
2.1.1. Absolute Maximum Ratings ............................................................................................... 10
2.1.2. Recommended Operation Conditions .............................................................................. 10
2.1.3. Power Consumption ......................................................................................................... 11
2.1.4. AC-Link Static Digital Specifications ................................................................................. 12
2.1.5. STAC9752 5 V Analog Performance Characteristics ....................................................... 12
2.1.6. STAC9753 3.3V Analog Performance Characteristics .....................................................14
2.2. AC Timing Characteristics ............................................................................................................... 16
2.2.1. Cold Reset ......................................................................................................................... 16
2.2.2. Warm Reset ....................................................................................................................... 16
2.2.3. Clocks ................................................................................................................................ 17
2.2.4. STAC9752/9753 Crystal Elimination Circuit and Clock Frequencies ................................17
2.2.5. Data Setup and Hold ........................................................................................................ 18
2.2.6. Signal Rise and Fall Times ............................................................................................... 18
2.2.7. AC-Link Low Power Mode Timing .................................................................................... 19
2.2.8. ATE Test Mode ................................................................................................................. 19
3. TYPICAL CONNECTION DIAGRAM .......................................................................................20
3.1. Slit Independent Power Supply Operation ...................................................................................... 21
4. CONTROLLER, CODEC AND AC-LINK .................................................................................23
4.1. AC-Link Physical Interface .............................................................................................................. 23
4.2. Controller to Single CODEC ............................................................................................................ 23
4.3. Controller to Multiple CODECs ........................................................................................................ 25
4.3.1. Primary CODEC Addressing ............................................................................................. 25
4.3.2. Secondary CODEC Addressing ........................................................................................ 25
4.3.3. CODEC ID Strapping ......................................................................................................... 26
4.4. Clocking for Multiple CODEC Implementations ............................................................................... 26
4.5. STAC9752/9753 as a Primary CODEC ........................................................................................... 26
4.5.1. STAC9752/9753 as a Secondary CODEC ........................................................................ 26
4.6. AC-Link Power Management ........................................................................................................... 27
4.6.1. Powering down the AC-Link .............................................................................................. 27
4.6.2. Waking up the AC-Link ...................................................................................................... 27
4.6.3. CODEC Reset ................................................................................................................... 28
5. AC-LINK DIGITAL INTERFACE ..............................................................................................29
5.1. Overview ......................................................................................................................................... 29
5.2. AC-Link Serial Interface Protocol .................................................................................................... 30
5.2.1. AC-Link Variable Sample Rate Operation ......................................................................... 30
5.2.2. Variable Sample Rate Signaling Protocol .......................................................................... 30
5.2.3. Primary and Secondary CODEC Register Addressing ...................................................... 32
5.3. AC-Link Output Frame (SDATA_OUT) ............................................................................................ 32
5.3.1. Slot 0: TAG / CODEC ID ................................................................................................... 34
5.3.2. Slot 1: Command Address Port ......................................................................................... 34
5.3.3. Slot 2: Command Data Port ............................................................................................... 35
5.3.4. Slot 3: PCM Playback Left Channel .................................................................................. 35
5.3.5. Slot 4: PCM Playback Right Channel ................................................................................ 35
5.3.6. Slot 5: Modem Line 1 Output Channel .............................................................................. 35
5.3.7. Slot 6 - 11: DAC ................................................................................................................. 35
IDT™
2 STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
REV 3.3 1206


Part Number STAC9753
Description (STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS
Maker IDT
Total Page 30 Pages
PDF Download

STAC9753 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 STAC9750 (STAC9750 / STAC9751) VALUE-LINE TWO-CHANNEL AC97 CODECS
IDT
2 STAC9751 (STAC9750 / STAC9751) VALUE-LINE TWO-CHANNEL AC97 CODECS
IDT
3 STAC9752 (STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS
IDT
4 STAC9752A (STAC9752A / STAC9753A) AC97 2.3 CODECS
IDT
5 STAC9753 (STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS
IDT
6 STAC9753A (STAC9752A / STAC9753A) AC97 2.3 CODECS
IDT
7 STAC9758 (STAC9758 / STAC9759) HIGH-PERFORMANCE 6-CHANNEL AC97 2.3 CODEC
IDT
8 STAC9759 (STAC9758 / STAC9759) HIGH-PERFORMANCE 6-CHANNEL AC97 2.3 CODEC
IDT
9 STAC975x Value Line Two Channel AC97 Codecs with Headphone Drive and SPDIF Output
SigmaTel





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy