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IK Semiconductor

IN74ACT109 Datasheet Preview

IN74ACT109 Datasheet

Dual J-K Positive-Edge-Triggered Flip-Flop

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Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
TECHNICAL DATA
IN74ACT109
The IN74ACT109 is identical in pinout to the LS/ALS109,
HC/HCT109. The IN74ACT109 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs with
the next low-to-high transition of the clock. Both Q to Q outputs are
available from each flip-flop.
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT109N Plastic
IN74ACT109D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4uP.PIcINNo81=6m=GVNCDC
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q Q
LH
X XX H L
HL
LL
X XX L H
X
X X H*
H*
HH
LL L H
HH
H L Toggle
HH
L H No Change
HH
HH H L
HH
L X X No Change
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
1




IK Semiconductor

IN74ACT109 Datasheet Preview

IN74ACT109 Datasheet

Dual J-K Positive-Edge-Triggered Flip-Flop

No Preview Available !

IN74ACT109
MAXIMUM RATINGS*
Symbol
Parameter
Value
VCC
VIN
VOUT
IIN
IOUT
ICC
PD
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
-0.5 to +7.0
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±20
±50
±50
750
500
Tstg Storage Temperature
-65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND)
TJ Junction Temperature (PDIP)
TA Operating Temperature, All Package Types
IOH Output Current - High
IOL Output Current - Low
tr, tf Input Rise and Fall Time *
(except Schmitt Inputs)
* VIN from 0.8 V to 2.0 V
VCC =4.5 V
VCC =5.5 V
Min Max Unit
4.5 5.5
V
0 VCC V
140 °C
-40 +85 °C
-24 mA
24 mA
0 10 ns/V
0 8.0
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2


Part Number IN74ACT109
Description Dual J-K Positive-Edge-Triggered Flip-Flop
Maker IK Semiconductor
Total Page 6 Pages
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