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IK Semiconductor

IW4012B Datasheet Preview

IW4012B Datasheet

Dual 4-Input NAND Gate

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TECHNICAL DATA
Dual 4-Input NAND Gate
High-Voltage Silicon-Gate CMOS
IW4012B
The IW4012B NAND gates provide the system designer with direct
emplementation of the NAND function.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4012BN Plastic
IW4012BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PINS 6, 8 = NO CONNECTION
PIN 14 =VCC
PIN 7 = GND
www.datasheet4u.com
NC = NO CONNECTION
FUNCTION TABLE
Inputs
Output
A B CD
Y
L X XX
H
X L XX
H
X XLX
H
X XXL
H
H H HH
L
X = don’t care
1




IK Semiconductor

IW4012B Datasheet Preview

IW4012B Datasheet

Dual 4-Input NAND Gate

No Preview Available !

IW4012B
MAXIMUM RATINGS*
Symbol
Parameter
Value
VCC
VIN
VOUT
IIN
PD
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
-0.5 to +20
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±10
750
500
PD Power Dissipation per Output Transistor
Tstg Storage Temperature
100
-65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mW
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA Operating Temperature, All Package Types
Min Max Unit
3.0 18
V
0 VCC V
-55 +125
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2


Part Number IW4012B
Description Dual 4-Input NAND Gate
Maker IK Semiconductor
Total Page 5 Pages
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