PZ5032-10A44 Description
INTRODUCTION This report describes a construction analysis of the Philips PZ5032-10A44 32 macrocell CPLD. Five devices packaged in 44-pin Plastic Leaded Chip Carriers (PLCCs) were received for the analysis. Devices were date coded 9622.
PZ5032-10A44 Key Features
- Twin-well CMOS process in an N substrate (no epi)
- Sub-micron gate lengths (0.35 micron N-channel and 0.4 micron P-channel)
- Tungsten plugs used under all metal layers
- 1Free Datasheet http://
- Devices were packaged in 44-pin J-lead Plastic Leaded Chip Carriers (PLCCs) for surface mount
PZ5032-10A44 Applications
- The leadframe was constructed of copper and plated externally with tin-lead solder and internally with silver