Integrated Silicon Solution Electronic Components Datasheet

IS25C16 Datasheet

(IS25C08 / IS25C16) 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

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IS25C08

IS25C16

8K-BIT/16K-BIT SPI SERIAL

ELECTRICALLY ERASABLE PROM

ISSI®

Preliminary Information

APRIL 2006

FEATURES

• Serial Peripheral Interface (SPI) Compatible

— Supports SPI Modes 0 (0,0) and 3 (1,1)

• Wide-voltage Operation

— Vcc = 1.8V to 5.5V

• Low power CMOS

— Active current less than 3.0 mA (2.5V)

— Standby current less than 2.0 µA (2.5V)

• Block Write Protection

— Protect 1/4, 1/2, or Entire Array

• 16 byte page write mode

— Partial page writes allowed

• 10 MHz Clock Rate (5V)

• Self timed write cycles (5 ms Typical)

• High-reliability

— Endurance: 1 million cycles per byte

— Data retention: 100 years

• Industrial and Automotive temperature ranges

• 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP, and chip scale

packages are available

• Lead-free available

DESCRIPTION

The IS25C08 and IS25C16 are electrically erasable

PROM devices that use the Serial Peripheral Interface

(SPI) for communications. The IS25C08 is 8Kbit

(1024x 8) and the IS25C16 is 16Kbit (2048 x 8). The

IS25C08/16 EEPROMs are offered in a wide operating

voltage range of 1.8V to 5.5V compatible with most

application voltages. ISSI designed the IS25C08/16 to

be an efficient SPI EEPROM solution. The devices are

packaged in 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP, and

8-ball CSP.

The functional features of the IS25C08/16 allow them to

be among the most advanced serial non-volatile memo-

ries available. Each device has a Chip-Select (CS) pin,

and a 3-wire interface of Serial Data In (SI), Serial Data

Out (SO), and Serial Clock (SCK). While the 3-wire

interface of the IS25C08/16 provides for high-speed

access, a HOLD pin allows the memories to ignore the

interface in a suspended state; later the HOLD pin re-

activates communication without re-initializing the serial

sequence. A Status Register facilitates a flexible write

protection mechanism, and a device-ready bit (RDY).

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Preliminary Information Rev. 00H

02/23/06

Integrated Silicon Solution Electronic Components Datasheet

IS25C16 Datasheet

(IS25C08 / IS25C16) 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

No Preview Available !

IS25C08

IS25C16

PIN CONFIGURATION

8-Pin DIP, SOIC, and TSSOP

CS 1

SO 2

WP 3

GND 4

8 VCC

7 HOLD

6 SCK

5 SI

ISSI ®

PIN DESCRIPTIONS

SCK

GND

VCC

HOLD

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Power

Write Protect

Suspends Serial Input

PIN DESCRIPTIONS

Serial Clock (SCK): This timing signal provides syn-

chronization between the microcontroller and IS25C08/

16. Op-Codes, byte addresses, and data are latched on

SI with a rising edge of the SCK. Data on SO is re-

freshed on the falling edge of SCK for SPI modes (0,0)

and (1,1).

Serial Data Input (SI): This is the input pin for all data

that the IS25C08/16 is required to receive.

Serial Data Output (SO): This is the output pin for all

data transmitted from the IS25C08/16.

Chip Select (CS): The CS pin activates the device.

Upon power-up, CS should follow Vcc. When the device

is to be enabled for instruction input, the signal requires

a High-to-Low transition. While CS is stable Low, the

master and slave will communicate via SCK, SI, and SO

signals. Upon completion of communication, CS must

be driven High. At this moment, the slave device may

start its internal write cycle. When CS is high, the

device enters a power-saving standby mode, unless an

internal write operation is underway. During this mode,

the SO pin becomes high impedance.

Write Protect (WP): The purpose of this input signal is

to initiate Hardware Write Protection mode. This mode

prevents the Block Protection bits and the WPEN bit in

the Status Register from being altered. To cause

Hardware Write Protection, WP must be Low at the same

time WPEN is 1. WP may be hardwired to Vcc or GND.

HOLD (HOLD): This input signal is used to suspend the

device in the middle of a serial sequence and temporarily

ignore further communication on the bus (SI, SO, SCK).

Together with Chip Select, the HOLD signal allows

multiple slaves to share the bus. The HOLD signal

transitions must occur only when SCK is Low, and be

held stable during SCK transitions. (See Figure 8 for

Hold timing) To disable this feature, HOLD may be

hardwired to Vcc.

2 Integrated Silicon Solution, Inc. — 1-800-379-4774

Preliminary Information Rev. 00H

02/23/06

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IS25C16 Datasheet

(IS25C08 / IS25C16) 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

IS25C16 Datasheet

(IS25C08 / IS25C16) 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM

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