IS41C16128 Datasheet | ISSI

DESCRIPTION ISSI ISSI® ® AUGUST 1998 FEATURES - Extended Data-Out (EDO) Page Mode access cycle - TTL patible inputs and outputs - Refresh Interval: 512 cycles/8 ms - Refresh Mode : RAS -Only, CAS -before-RAS (CBR), and Hidden - JEDEC standard pinout - Single +5V ± 10% power supply - Byte Write and Byte Read operation via two CAS - Available in 40-pin SOJ and TSOP (Type II) - Industrial temperature available The ISSI IS41C16128 is a 131,072 x 16-bit high-performance CMOS Dynamic Random Access Memory. The IS41C16128 offers an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 256 random accesses within a single row with access cycle time as short as 12 ns per 16bit word. The Byte Write control, of upper and lower byte, makes the IS41C16128 ideal for use in 16-, 32-bit wide data bus systems. These features make the IS41C16128 ideally suited for high band-width graphics, digital signal processing, high-performance puting systems, and peripheral applications. The IS41C16128 is packaged in a 40-pin 400-mil SOJ and TSOP (Type II). FUNCTIONAL BLOCK DIAGRAM OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC OE RAS CLOCK GENERATOR DATA I/O BUS REFRESH COUNTER DATA I/O BUFFERS ROW DECODER COLUMN DECODERS SENSE AMPLIFIERS I/O0-I/O15 MEMORY ARRAY 131,072 x 16 ADDRESS BUFFERS A0-A8 This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. PRELIMINARY DR002-1D 08/20/98 KEY TIMING PARAMETERS Parameter Max. RAS Access Time (t RAC) Max. CAS Access Time (t CAC) Max. Column Address Access Time (t AA) Min. EDO Page Mode Cycle Time (t PC) Min. Read/Write Cycle Time (t RC) -35 35 ns 10 ns 18 ns 12 ns 60 ns -40 40...