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Integrated Silicon Solution Electronic Components Datasheet

IS42R83200D Datasheet

256-MBIT SYNCHRONOUS DRAM

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IS42R83200D, IS42R16160D
IS45R83200D, IS45R16160D
32Meg x 8, 16Meg x16
256-MBIT SYNCHRONOUS DRAM
MARCH 2010
FEATURES
• Clock frequency: 133, 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 2.5V + 0.2V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 16 ms (A2 grade) or
64 ms (commercial, industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP-II (x8 and x16)
54-ball BGA (x16 only)
• Operating Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
OVERVIEW
ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
IS42/45R83200D IS42/45R16160D
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball BGA
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-75
7.5
10
133
100
5.4
6
Unit
ns
ns
Mhz
Mhz
ns
ns
ADDRESS TABLE
Parameter
32M x 8
Configuration
8M x 8 x 4
banks
Refresh Count
Com./Ind.
A1
A2
8K/64ms
8K/64ms
8K/16ms
Row Addresses
A0-A12
Column Addresses
A0-A9
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
16M x 16
4M x 16 x 4
banks
8K/64ms
8K/64ms
8K/16ms
A0-A12
A0-A8
BA0, BA1
A10/AP
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
03/02/2010
1


Integrated Silicon Solution Electronic Components Datasheet

IS42R83200D Datasheet

256-MBIT SYNCHRONOUS DRAM

No Preview Available !

IS42R83200D, IS42R16160D
IS45R83200D, IS45R16160D
DEVICE OVERVIEW
The 256Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 2.5V Vdd
and 2.5V Vddq memory systems containing 268,435,456
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 67,108,864-bit bank is orga-
nized as 8,192 rows by 512 columns by 16 bits or 8,192
rows by 1,024 columns by 8 bits.
The 256Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 256Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled.  Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A12 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (For 4Mx16x4 Banks SHOWN)
CLK
CKE
CS
RAS
CAS
WE
A10
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
13
ROW
ADDRESS
13 LATCH
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
13
13
DATA IN
BUFFER
16 16
2
DQML
DQMH
DQ 0-15
DATA OUT
BUFFER
16 16
VDD/VDDQ
Vss/VssQ
8192
8192
8192
8192
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
BURST COUNTER
COLUMN
ADDRESS BUFFER
BANK CONTROL LOGIC
512
(x 16)
COLUMN DECODER
9
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
03/02/2010


Part Number IS42R83200D
Description 256-MBIT SYNCHRONOUS DRAM
Maker ISSI
Total Page 30 Pages
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