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IS42RM32200M - 512K x 32Bits x 4Banks Mobile Synchronous DRAM

Download the IS42RM32200M datasheet PDF. This datasheet also covers the IS42VM32200M variant, as both devices belong to the same 512k x 32bits x 4banks mobile synchronous dram family and are provided as variant models within a single manufacturer datasheet.

General Description

These IS42SM/RM/VM32200M are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 524,288 words x 32 bits.

These products are offering fully synchronous operation and are referenced to a positive edge of the clock.

Key Features

  • JEDEC standard 3.3V, 2.5V, 1.8V power supply.
  • Auto refresh and self refresh.
  • All pins are compatible with LVCMOS interface.
  • 4K refresh cycle / 64ms.
  • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst.
  • Programmable CAS Latency : 2,3 clocks.
  • All inputs and outputs referenced to the positive edge of the system clock.
  • Data mask function by DQM.
  • Internal 4.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS42VM32200M-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS42R32200C1 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM Integrated Silicon Solution
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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS42RM32200K 512K x 32Bits x 4Banks Mobile Synchronous DRAM
IS42RM32100C 512K x 32Bits x 2Banks Low Power Synchronous DRAM
IS42RM32100D 512K x 32Bits x 2Banks Low Power Synchronous DRAM
IS42RM32160C 512Mb Mobile Synchronous DRAM
IS42RM32160E 4M x 32Bits x 4Banks Mobile Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS42/45SM/RM/VM32200M 512K x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42SM/RM/VM32200M are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features  JEDEC standard 3.3V, 2.5V, 1.