taS Single 3.3V (± 0.3V) power supply
a High speed clock cycle time -7: 133MHz<3-3-3>,
w Fully synchronous operation referenced to clock
w Possible to assert random column access in
Quad internal banks contorlled by A12 & A13
.c Byte control by LDQM and UDQM for
U Programmable Wrap sequence (Sequential /
Programmable burst length (1, 2, 4, 8 and full
Programmable /CAS latency (2 and 3)
e Automatic precharge and controlled precharge
h CBR (Auto) refresh and self refresh
S X8, X16 organization
LVTTL compatible inputs and outputs
ta 4,096 refresh cycles / 64ms
a Burst termination by Burst stop and Precharge
.D Package 400mil 54-pin TSOP-2
The IS42S8800 and IS42S16400 are high-speed 67,
108,864-bit synchronous dynamic random-access
moeories, organized as 2,097,152 x 8 x 4 and 1,048,
576 x 16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data
transfer using the pipeline architecture and clock
frequency up to 133MHz for -7. All input and outputs
are synchronized with the postive edge of the clock.
The synchronous DRAMs are compatible with Low
Voltage TTL (LVTTL).These products are pack-aged
in 54-pin TSOP-2.
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