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Integrated Silicon Solution Electronic Components Datasheet

IS42S16400C1 Datasheet

1M-Bit x 16-Bit 4 4-Bank SDRAM

No Preview Available !

®
I1SM4e2gSB1it6s4x0t1406UCB.ci1otsmx 4 Banks (64-MBIT) ISSIOCTOBER 2005
SYNCHtaRSOhNeeOUS DYNAMIC RAMFEATURES
a• Clock frequency: 166, 143 MHz
.D• Fully synchronous; all signals referenced to a
wpositive clock edge
w• Internal bank for hiding row access/precharge
w• Single 3.3V power supply
m• LVTTL interface
o• Programmable burst length
.c– (1, 2, 4, 8, full page)
• Programmable burst sequence:
USequential/Interleave
t4• Self refresh modes
• 4096 refresh cycles every 64 ms
e• Random column address every clock cycle
e• Programmable CAS latency (2, 3 clocks)
h• Burst read/write and burst read/single write
operations capability
S• Burst termination by burst stop and precharge
tacommand
• Byte controlled by LDQM and UDQM
a• Industrial temperature availability
• Package: 400-mil 54-pin TSOP II
.D• Lead-free package is available
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S16400C1 is
organized as 1,048,576 bits x 16-bit x 4-bank for improved
performance. ThesynchronousDRAMsachievehigh-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VDD
DQ0
VDDQ
DQ1
DQ2
GNDQ
DQ3
DQ4
VDDQ
DQ5
DQ6
GNDQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 GND
53 DQ15
52 GNDQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 GNDQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 GND
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 GND
wPIN DESCRIPTIONS
wA0-A11
w omBA0, BA1
.cDQ0 to DQ15
t4UCLK
eCKE
heCS
SRAS
ataCAS
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
VDD
GND
VDDQ
GNDQ
NC
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
.DCopyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
wany published information and before placing orders for products.
wwIntegrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. E
10/25/05


Integrated Silicon Solution Electronic Components Datasheet

IS42S16400C1 Datasheet

1M-Bit x 16-Bit 4 4-Bank SDRAM

No Preview Available !

IS42S16400C1
ISSI ®
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 4,096
rows by 256 columns by 16 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one
of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The READ or
WRITE commands in conjunction with address bits reg-
istered are used to select the starting column location for
the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
12
ROW
ADDRESS
12 LATCH
COLUMN
ADDRESS LATCH
8
BURST COUNTER
COLUMN
ADDRESS BUFFER
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
12
DATA IN
BUFFER
16 16
DQM
DQ 0-15
DATA OUT
BUFFER
16 16
VDD/VDDQ
GND/GNDQ
4096
4096
4096
MEMORY CELL
12
4096
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
256K
(x 16)
COLUMN DECODER
8
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
10/25/05


Part Number IS42S16400C1
Description 1M-Bit x 16-Bit 4 4-Bank SDRAM
Maker ISSI
Total Page 30 Pages
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