IS43DR16320D Datasheet | ISSI

IS43/46DR86400D IS43/46DR16320D 64Mx8, 32Mx16 DDR2 DRAM Features - Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V - JEDEC standard 1.8V I/O (SSTL_18-patible) - Double data rate interface: two data transfers per clock cycle - Differential data strobe (DQS, DQS) - 4-bit prefetch architecture - On chip DLL to align DQ and DQS transitions with CK - 4 internal banks for concurrent operation - Programmable CAS latency (CL) 3, 4, 5, and 6 supported - Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported - WRITE latency = READ latency - 1 t CK - Programmable burst lengths: 4 or 8 - Adjustable data-output drive strength, full and reduced strength options - On-die termination (ODT) JANUARY 2015 DESCRIPTION ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. ADDRESS TABLE Parameter 64M x 8 32M x 16 Configuration 16M x 8 x 4 8M x 16 x 4 banks banks Refresh Count 8K/64ms 8K/64ms Row Addressing 16K (A0-A13) 8K...