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IS43DR16320D Datasheet DDR2 DRAM

Manufacturer: ISSI (now Infineon)

Overview: IS43/46DR86400D IS43/46DR16320D 64Mx8, 32Mx16 DDR2 DRAM.

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General Description

ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

ADDRESS TABLE Parameter 64M x 8 32M x 16 Configuration 16M x 8 x 4 8M x 16 x 4 banks banks Refresh Count 8K/64ms 8K/64ms Row Addressing 16K (A0-A13) 8K (A0-A12) Column Addressing 1K (A0-A9) 1K (A0-A9) Bank Addressing BA0, BA1 BA0, BA1 Precharge A10 A10 Addressing OPTIONS • Configuration(s): 64Mx8 (16Mx8x4 banks) IS43/46DR86400D 32Mx16 (8Mx16x4 banks) IS43/46DR16320D • Package: x8: 60-ball BGA (8mm x 10.5mm) x16: 84-ball WBGA (8mm x 12.5mm) • Timing – Cycle time 2.5ns @CL=5 DDR2-800D 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D 3.75ns @CL=4 DDR2-533C 5ns @CL=3 DDR2-400B • Temperature Range: Commercial (0°C ≤ Tc ≤ 85°C) Industrial (-40°C ≤ Tc ≤ 95°C;

Key Features

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V.
  • JEDEC standard 1.8V I/O (SSTL_18-compatible).
  • Double data rate interface: two data transfers per clock cycle.
  • Differential data strobe (DQS, DQS).
  • 4-bit prefetch architecture.
  • On chip DLL to align DQ and DQS transitions with CK.
  • 4 internal banks for concurrent operation.
  • Programmable CAS latency (CL) 3, 4, 5, and 6 supported.
  • Posted CAS and programmable additive latency (AL) 0,.

More Datasheets from ISSI (now Infineon)

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IS43DR16640C DDR2 DRAM
IS43DR16640D 64Mx16 DDR2 DRAM
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