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IS43LR16128B - 2Gb Mobile DDR SDRAM

Download the IS43LR16128B datasheet PDF. This datasheet also covers the IS46LR32640B variant, as both devices belong to the same 2gb mobile ddr sdram family and are provided as variant models within a single manufacturer datasheet.

Description

The IS43/46LR16128B/32640B is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 128Meg words of 16bits or 64Meg words of 32bits.

This product uses a double-data-rate architecture to achieve high-speed operation.

Features

  • JEDEC standard 1.8V power supply.
  • VDD = 1.8V, VDDQ = 1.8V.
  • Four internal banks for concurrent operation.
  • MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8) - Burst type (sequential & interleave).
  • Fully differential clock inputs (CK, /CK).
  • All inputs except data & DM are sampled at the rising edge of the system clock.
  • Data I/O transaction on both edges of data strobe.
  • Bidirectional data.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS46LR32640B-ISSI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS43LR16160F 4M x 16Bits x 4Banks Mobile DDR SDRAM
IS43LR16160G 4M x 16Bits x 4Banks Mobile DDR SDRAM
IS43LR16200C 1M x 16Bits x 2Banks Mobile DDR SDRAM
IS43LR16200D 1M x 16Bits x 2Banks Mobile DDR SDRAM
IS43LR16320B 8M x 16Bits x 4Banks Mobile DDR SDRAM

Full PDF Text Transcription

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IS43/46LR32640B IS43/46LR16128B 2Gb (x16, x32) Mobile DDR SDRAM Preliminary Information Description SEPTEMBER 2022 The IS43/46LR16128B/32640B is 2,147,483,648 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 128Meg words of 16bits or 64Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit or 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
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