IS43LR16320B Datasheet PDF (8M x 16Bits x 4Banks Mobile DDR SDRAM)

IS43LR16320B - 8M x 16Bits x 4Banks Mobile DDR SDRAM

Description

The IS43/46LR16320B is a 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 8,388,608 words x 16 bits.

This product uses a double-data-rate architecture to achieve high-speed operation.

The Data Input/ Output signals are transmitted on a 16bit bus.

Features

JEDEC standard 1.8V power supply.
VDD = 1.8V, VDDQ = 1.8V.
Four internal banks for concurrent operation.
MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave).
Fully differential clock inputs (CK, /CK).
All inputs except data & DM are sampled at the rising edge of the system clock.
Data I/O transaction on both edges of data strobe.
Bidirectional d.

Datasheet Details

Part number	IS43LR16320B
Manufacturer	ISSI
File Size	1.54 MB
Description	8M x 16Bits x 4Banks Mobile DDR SDRAM
Datasheet	IS43LR16320B Datasheet
Additional preview pages of the IS43LR16320B datasheet.

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Full PDF Text Transcription

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IS43LR16320B, IS46LR16320B 8M x 16Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR16320B is a 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 8,388,608 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

Published: Jun 28, 2016 |