IS46LQ16256AL Datasheet | ISSI

IS43/46LQ16256A, IS43/46LQ16256AL IS43/46LQ32128A, IS43/46LQ32128AL ® Long-term Support World Class Quality 4Gb (x16/x32) Mobile LPDDR4/LPDDR4X Features - Configuration: - 256Mb x16 x 1 channel - 128Mb x 16 x 2 channels - 8 internal banks per channel - Low-voltage Core and I/O Power Supplies VDD1 = 1.70-1.95V VDD2 = 1.06-1.17V VDDQ = 1.06-1.17V (LPDDR4) VDDQ = 0.57-0.65V (LPDDR4X) - LVSTL(Low Voltage Swing Terminated Logic) I/O Interface - Internal VREF and VREF Training - Dynamic ODT : DQ ODT :VSSQ Termination CA ODT :VSS Termination - Max. Clock Frequency : 1.6GHz (3.2Gbps) - 16n Pre-fetch DDR architecture - Single data rate (multiple cycles) mand/ address bus - Bidirectional/differential data strobe per byte of data (DQS/DQS#) - Programmable burst lengths (16 or 32) - ZQ Calibration - Operation Temperature Industrial (TC = -40°C to 95°C) Automotive, A1 (TC = -40°C to 95°C) Automotive, A2 (TC = -40°C to 105°C) Automotive, A3 (TC = -40°C to 125°C) - Clock-Stop capability JANUARY 2024 DESCRIPTION The IS43/46LQ16256A/AL and IS43/46LQ32128A/AL are 4Gbit CMOS LPDDR4 SDRAM. The device is organized as 1/2 channels per device, and each channel is 8-banks and 16-bits. This product uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. - On-chip temperature sensor whose status can be read from MR4 - 200-ball x16/x32 BGA (10x14.5mm) in Green Package ADDRESS TABLE Parameter # of...