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IS61LPS12836EC - SINGLE CYCLE DESELECT SRAM

General Description

The 4Mb product family

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Single cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS61LPS12836A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS12832A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS102418B SINGLE CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS102436A 36Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution
IS61LPS204818A 36Mb Single CYCLE DESELECT STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61LPS12832EC SINGLE CYCLE DESELECT SRAM
IS61lPS102418A 18Mb Single CYCLE DESELECT STATIC RAM
IS61LPS102436B 36Mb Single CYCLE DESELECT STATIC RAM
IS61LPS204818B 36Mb Single CYCLE DESELECT STATIC RAM
IS61LPS25618EC SINGLE CYCLE DESELECT SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM APRIL 2017 FEATURES  Internal self-timed write cycle  Individual Byte Write Control and Global Write  Clock controlled, registered address, data and control  Burst sequence control using MODE input  Three chip enable option for simple depth expansion and address pipelining  Common data inputs and data outputs  Auto Power-down during deselect  Single cycle deselect  Snooze MODE for reduced-power standby  JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages  Power supply: LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) VPS: VDD 2.5V (± 5%), VDDQ 2.