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IS61NVP10018 Datasheet (IS61NVP10018 / IS61NVP51236) State Bus SRAM

Manufacturer: ISSI (now Infineon)

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General Description

® PRELIMINARY INFORMATION SEPTEMBER 2002 The 18 Meg 'NVP' product family

Overview

IS61NVP51236 IS61NVP10018 512K x 36 and 1M x 18 PIPELINE 'NO WAIT' STATE BUS.

Key Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle www. DataSheet4U. com.
  • Individual Byte Write Control.
  • Single R/W (Read/Write) control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control using MODE input.
  • Three chip enables for simple depth expansion and address pipelining for TQFP.
  • Power Down mode.
  • Commo.

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IS61NVP25636A 9Mb STATE BUS SRAM
IS61NVP25636B 9Mb STATE BUS SRAM
IS61NVP25672 (IS61NVPxxxxx) STATE BUS SRAM
IS61NVP51218A 9Mb STATE BUS SRAM
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