Download the IS61QDB41M36A datasheet PDF.
This datasheet also covers the IS61QDB42M18A variant, as both devices belong to the same 36mb quad synchronous sram family and are provided as variant models within a single manufacturer datasheet.
General Description
APRIL 2016
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Full PDF Text Transcription for IS61QDB41M36A (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
IS61QDB41M36A. For precise diagrams, and layout, please refer to the original PDF.
IS61QDB42M18A IS61QDB41M36A 2Mx18, 1Mx36 36Mb QUAD (Burst 4) SYNCHRONOUS SRAM FEATURES DESCRIPTION APRIL 2016 1Mx36 and 2Mx18 configuration available. On-chip Delay-L...
View more extracted text
PRIL 2016 1Mx36 and 2Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneousl
IS61QDB41M36A Datasheet
