IS61QDB42M18 Overview
The 36Mb IS61QDB41M36 and IS61QDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
IS61QDB42M18 Key Features
- 1M x 36 or 2M x 18
- On-chip delay-locked loop (DLL) for wide data valid window
- Separate read and write ports with concurrent read and write operations
- Synchronous pipeline read with late write operation
- Double data rate (DDR) interface for read and write input ports
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K) for address and control registering at rising edges only
- Two input clocks (C and C) for data output control
- Two echo clocks (CQ and CQ) that are delivered simultaneously with data