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IS61QDB42M18 Datasheet 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs

Manufacturer: ISSI (now Infineon)

Download the IS61QDB42M18 datasheet PDF. This datasheet also includes the IS61QDB41M36 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (IS61QDB41M36-ISSI.pdf) that lists specifications for multiple related part numbers.

General Description

The 36Mb IS61QDB41M36 and IS61QDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Overview

36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs .

Key Features

  • 1M x 36 or 2M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Separate read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double data rate (DDR) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges o.