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IS61QDB42M36 - QUAD (Burst of 4) Synchronous SRAMs

General Description

The 72Mb IS61QDB42M36 and IS61QDB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Key Features

  • 2M x 36 or 4M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Separate read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double data rate (DDR) interface for read and write input ports.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges o.

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Full PDF Text Transcription for IS61QDB42M36 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61QDB42M36. For precise diagrams, and layout, please refer to the original PDF.

72 Mb (2M x 36 & 4M x 18) Q7 UAD (Burst o. f 4) Synchronous SRAMs Q November 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid win...

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or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation. • Double data rate (DDR) interface for read and write input ports. • Fixed 4-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. • Industrial temperature available • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5,