Download the IS61QDB42M36A datasheet PDF.
This datasheet also covers the IS61QDB44M18A variant, as both devices belong to the same 72mb quad (burst 4) synchronous sram family and are provided as variant models within a single manufacturer datasheet.
General Description
AUGUST 2014
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Full PDF Text Transcription for IS61QDB42M36A (Reference)
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IS61QDB42M36A. For precise diagrams, and layout, please refer to the original PDF.
IS61QDB44M18A IS61QDB42M36A 4Mx18, 2Mx36 72Mb QUAD (Burst 4) SYNCHRONOUS SRAM FEATURES DESCRIPTION AUGUST 2014 2Mx36 and 4Mx18 configuration available. On-chip Delay-...
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UGUST 2014 2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneous
IS61QDB42M36A Datasheet
