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IS61QDP2B22M18A1 - 36Mb QUADP (Burst 2) Synchronous SRAM

Download the IS61QDP2B22M18A1 datasheet PDF. This datasheet also covers the IS61QDP2B22M18A variant, as both devices belong to the same 36mb quadp (burst 2) synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

devices.

need for high-speed bus turnaround.

operations are self-timed.

Key Features

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.0 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and cont.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDP2B22M18A-ISSI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for IS61QDP2B22M18A1 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for IS61QDP2B22M18A1. For precise diagrams, and layout, please refer to the original PDF.

IS61QDP2B22M18A/A1/A2 IS61QDP2B21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM (2.0 CYCLE READ LATENCY) JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configurat...

View more extracted text
CYCLE READ LATENCY) JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.

More Datasheets from ISSI (now Infineon)

Part Number Description
IS61QDP2B22M18A 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B22M18A2 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B22M36A 72Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B22M36A1 72Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B22M36A2 72Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M18A 18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M18A1 18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M18A2 18Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M36A 36Mb QUADP (Burst 2) Synchronous SRAM
IS61QDP2B21M36A1 36Mb QUADP (Burst 2) Synchronous SRAM